Low-Power Phase Frequency Detector Using Hybrid AVLS and LECTOR Techniques for Low-Power PLL

Abstract

Wireless communication is a fast-growing industry and recent developments focus on improving certain aspects of the area and reducing the power con- sumption while maintaining the frequency of operation. Phase Locked Loop (PLL) is an integral part of commu- nication circuits which operate at very high frequencies. Phase Frequency Detector (PFD) is the first block of PLL and is key in determining the computational ca- pacity of the PLL. The power consumption of the PFD has to be reduced to minimize the overall power con- sumption of PLL. The PFD architecture used is based on Double Edged Triggered D Flip-Flop (DET-DFF), which is free of dead zone. Stack, LECTOR, AVLS and hybrid low-power approaches are implemented to reduce the power consumption of DET-DFF based PFD architectures. The PFDs power, delay and power delay product analysis is performed using Cadence Virtuoso and Spectre in CMOS 180 nm and 90 nm technology. A power reduction of upto 32 % has been observed while keeping the transistor count to a minimum