On the Reuse of RTL assertions in Systemc TLM Verification

Reuse of existing and already verified intellectual property (IP) models is a key strategy to cope with the com- plexity of designing modern system-on-chips (SoC)s under ever stringent time-to-market requirements. In particular, the recent trend towards system-level design and transaction level modeling (TLM) gives rise to new challenges for reusing existing RTL IPs and their verification environment in TLM-based design flows. While techniques and tools to abstract RTL IPs into TLM models have begun to appear, the problem of reusing, at TLM, a verification environment originally developed for an RTL IP is still underexplored, particularly when assertion-based verification (ABV) is adopted. Some techniques and frameworks have been proposed to deal with ABV at TLM, but they assume a top-down design and verification flow, where assertions are defined ex-novo at TLM level. In contrast, the reuse of existing assertions in an RTL-to-TLM bottom-up design flow has not been analyzed yet. This paper proposes a methodology to reuse assertions originally defined for a given RTL IP, to verify the corresponding TLM model. Experimental results have been conducted on benchmarks of different characteristics and complexity to show the applicability and the efficacy of the proposed methodology

Symbad: Formal Verification in System Level-based Design

The paper presents the SYMBAD project: a system level design and verification framework for HW and SW integrated systems. Such a framework leads to a new methodology in high-level system design which joins different formal and dynamic verification strategies

A testbench specification language for SystemC Verification

Testing of embedded systems, operating in the real environment, is generally performed by using an industrial test bench that stimulates the system through sensors and human-machine interfaces. The test bench provides the engineers with a set of tools for reproducing the environmental conditions which may affect the system. On the contrary, a different approach is adopted at the early stages of the design flow, when system level languages, like SystemC, are used to describe the functionality of the design. At this level, stimuli for testing the design are traditionally generated in a random or statistical way, which makes more difficult to capture well-specific behaviors of the considered environment, thus decreasing the effectiveness and the efficiency of the verification. This is particularly evident for dynamic assertion-based verification where, to avoid vacuous passes of assertions, stimuli must reflect specific scenarios to activate the assertions. In this work, we propose a graphical framework to automatically generate stimuli, particularly suited to be used for dynamic ABV of embedded SW. The framework relies on the definition of a Testbench Specification Language (TSL) that allows to formally capture the behavior of the real environment where embedded SW is intended to be executed, i.e., how input values evolve on time intervals. Then, the framework allows to automatically synthesize TSL descriptions into SystemC-based stimuli generators, which exploit and extend the functionality of the SystemC Verification Library

Efficient fault injection in QEMU

Early analysis of software dependability and fault tolerance properties requires an efficient and effective fault modelling environment before the physical prototype of the target platform is available. In this context, fault injection on cycle- accurate models implemented by means of Hardware Descrip- tion Languages (HDLs) is a quite common and valid solution. However, cycle-accurate simulation has revealed to be too time- consuming when the objective is to emulate the effect of soft errors on complex microprocessors. To address this issue, the paper presents an efficient fault injection approach based on QEMU, which is one of the most efficient and popular instruction- accurate emulator for several microprocessor architectures. As main goal, the proposed approach represents a non intrusive technique that minimizes the impact of the fault injection procedure in the emulator performance. Experimental results for both x86 and ARM processors considering permanent and transient/intermittent faults are presented

Fostering Human Activity Recognition Workflows: An Open-Source Baseline Framework

The application of machine and deep learning algorithms in Human Activity Recognition (HAR) has shown great potential for monitoring various professional and daily life activities, benefiting different research areas such as healthcare, well-being and industrial automation. HAR can enable the development of various services and applications to empower technical performance and enable risk prevention in working places, to support education and training, and, more in general, to monitor the biopsychosocial status of people. However, we still lack a baseline framework for easily implementing the data processing pipeline that must be designed to setup and configure HAR workflows. This makes challenging to estimate the effectiveness, efficiency, and the overall quality of HAR solutions, thus hindering the comparison among different approaches. This also increases the likelihood that researchers introduce errors, which negatively affect the accuracy of the obtained results. To fill in the gap, this paper introduces B-HAR, an open-source framework to automatically implement baseline HAR workflows

Incremental ABV for Functional Validation of TL-to-RTL Design Refinement

Transaction-level modeling (TLM) has been proposed as the leading strategy to address the always increasing complexity of digital systems. However, its introduction arouses a new challenge for designers and verification engineers, since there are no mature tools to automatically synthesize an RTL implementation from a transaction-level (TL) design, thus manual refinements are mandatory. In this context, the paper presents an incremental assertion-based verification (ABV) methodology to check the correctness of the TL-to-RTL refinement. The methodology relies on reusing assertions and already checked code, and it is guided by an assertion coverage metric

Incremental ABV for TL-to-RTL Design Refinement

Transaction-level modeling (TLM) has been proposed as the leading strategy to address the always increasing complexity of digital systems. However, its introduction arouses a new challenge for designers and verification engineers, since no tools are available to automatically derive an RTL implementation from a transaction-level (TL) design, thus manual refinements are mandatory. In this context, the paper presents an incremental assertion-based verification (ABV) methodology to check the correctness of the TL-to-RTL refinement. The methodology relies on reusing TL assertions and TL code and it is guided by a assertion coverage metrics

Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions

Transaction-level modeling (TLM) is the most promising technique to deal with the increasing complexity of modern embedded systems. However, modeling a complex system completely at transaction level could be inconvenient when IP cores are available on the market, since they are usually modeled at register transfer level (RTL). In this context, modeling and verification methodologies based on transactors allow designers to reuse RTL IPs into TLM-RTL mixed designs, thus guaranteeing a considerable saving of time. Practical advantages of such an approach are evident, but mixed TLM-RTL designs cannot completely provide the well-known effectiveness in terms of simulation speed provided by TLM. This paper presents a methodology to automatically abstract RTL IPs into equivalent TLM descriptions. To do that, the paper first proposes a formal definition of equivalence based on events, showing how such a definition can be applied to prove the correctness of a code manipulation methodology, such as code abstraction. Then, the paper proposes a technique to automatically abstract RTL IPs into TLM descriptions. Finally, the paper shows that the TLM descriptions obtained by applying the proposed technique are correct by construction, relying on the given definition of event-based equivalence. A set of experimental results is reported to confirm the effectiveness of the methodology

A Methodology for Abstracting RTL Designs into TL Descriptions

Transaction-level modeling (TLM) has been proposed as the leading strategy to address the always increasing complexity of digital systems. However, modeling a complex system completely at transaction level (TL) could be inconvenient when IP cores are available on the market, usually modeled at RT level. In this context, modeling and verification methodologies based on transactors allow one to reuse RTL IP-cores in TL-RTL mixed designs, thus guaranteeing a considerable saving of time. Even if practical advantages of such an approach are evident, mixed TL-RTL designs cannot completely benefit from the well-known effectiveness provided by TLM. Thus, this paper proposes a methodology to abstract RTL IPs into corresponding TL descriptions. The possibility of automating the methodology is deeply analyzed. In particular, the paper shows which abstraction levels can be reached without requiring human intervention, according to the characteristics of the design to be refined. A set of experimental results are finally reported to confirm the effectiveness of the methodolog