Prebiotic lactulose as efficacious microbiota and metabolite modulator in cirrhosis environment

8openItalian coauthor/editoropenMancini, A.; Larsen, S.; Campagna, F.; Franceschi, P.; Amodio, P.; Pravadelli, C.; Pindo, M; Tuohy, K.Mancini, A.; Larsen, S.; Campagna, F.; Franceschi, P.; Amodio, P.; Pravadelli, C.; Pindo, M.; Tuohy, K

Fostering Human Activity Recognition Workflows: An Open-Source Baseline Framework

The application of machine and deep learning algorithms in Human Activity Recognition (HAR) has shown great potential for monitoring various professional and daily life activities, benefiting different research areas such as healthcare, well-being and industrial automation. HAR can enable the development of various services and applications to empower technical performance and enable risk prevention in working places, to support education and training, and, more in general, to monitor the biopsychosocial status of people. However, we still lack a baseline framework for easily implementing the data processing pipeline that must be designed to setup and configure HAR workflows. This makes challenging to estimate the effectiveness, efficiency, and the overall quality of HAR solutions, thus hindering the comparison among different approaches. This also increases the likelihood that researchers introduce errors, which negatively affect the accuracy of the obtained results. To fill in the gap, this paper introduces B-HAR, an open-source framework to automatically implement baseline HAR workflows

An EFSM-based Approach for Functional ATPG

This paper presents an EFSM-based approach for functional automatic test pattern generation (ATPG). It shows how a particular kind of extended FSM (EFSM) can be efficiently traversed by a pseudo-determinist ATPG to control and propagate faults for a functional description of a design. Functional ATPG on such EFSM models have been showed to be more efficient than the ATPG on the original design. However, test sequences generated on such an EFSM can lose their efficacy when simulated on the original description, since they may show some timing discrepancies. To solve this problem, this paper propose a strategy that manipulates the EFSM model

Functional Verification based on the EFSM Model

The paper presents a methodology for addressing hard-to-detect faults when a high-level ATPG is applied to verify functional descriptions of sequential circuits. A particular kind of extended finite state machines is adopted to improve detectability of such faults

Functional Fault Coverage: the Chamber of Secrets or an Accurate Estimation of Gate-Level Coverage?

More and more functional verification is attracting EDA researchers and industrial companies interested in digital system validation. Coverage metrics and functional fault models are used to guide the generation of functional tests achieving high fault coverage in a relatively short time with respect to traditional gate-level ATPGs. However, what is the effectiveness of test sequences generated at functional level with respect to the more traditional gate-level stuck at fault model? The paper presents an accurate analysis of the correlation between the high-level bit coverage fault model and the gate-level stuck-at fault model

Logic-Level Mapping of High-Level Faults

Many high-level fault models have been proposed in the past to perform verification at functional level, however high-level automatic test pattern generators (ATPGs) are still in a prototyping phase, while very efficient logic-level ATPGs are available. On the other side, coverage metrics and functional fault models are used to guide the generation of functional tests achieving high fault coverage in a relatively short time with respect to traditional gate-level ATPGs. However, what is the effectiveness of test sequences generated at functional level with respect to the more traditional gate-level stuck-at fault model? The paper presents an accurate analysis of the correlation between high-level fault models and the gate-level stuck-at fault model and it proposes a strategy to map high-level faults into logic-level faults. Thus, functional verification, based on a high-level fault model, can be performed by exploiting the capability of state of the art logic-level ATPGs. Experimental results highlight the effectiveness of the methodolog

A CLP-based Functional ATPG for Extended FSMs

It is a common opinion that semi-formal verification offers a good compromise between speed and exhaustiveness. In this context, the paper presents a semi-formal functional ATPG that joins static and dynamic techniques to generate high-quality test sequences. The ATPG works on a set of concurrent extended finite state machines (EFSMs) that models the design under verification (DUV). The test generation procedure relies on backjumping, for traversing the EFSM transitions, and constraint logic programming (CLP), for covering corner cases through the deterministic propagation of functional faults observed, but not detected, during the transition traversal