Impact of Line Resistance Combined with Device Variability on Resistive RAM Memories

International audienceIn this paper, the performance and reliability of oxide-based Resistive RAM (ReRAM) memory is investigated in a 28nm FDSOI technology versus interconnects resistivity combined with device variability. Indeed, common problems with ReRAM are related to high variability in operating conditions and low yield. At a cell level ReRAMs suffer from variability. At an array level, ReRAMs suffer from different voltage drops seen across the cells due to line resistances. Although research has taken steps to resolve these issues, variability combined with resistive paths remain an important characteristic for ReRAMs. In this context, a deeper understanding of the impact of these characteristics on ReRAM performances is needed to propose variability tolerant designs to ensure the robustness of the technology. The presented study addresses the memory cell, the memory word up to the memory matrix

A global modeling approach of the leakage phenomena in dielectrics

Thanks to its low noise level, the LSBB environment provides particular environment to carry out high quality electrical characterizations. In this paper, we propose a complete modeling approach of the experimental results from our experimental microelectronic setup. The tested device is a Metal Oxide Semiconductor (MOS) floating gate capacitor which can be found in electrostatic non volatile memories such as Flash. The main idea is to characterize and model the leakage current through the tunnel oxide. We proposed, in a previous work, a model for charge loss considering a fractional Poisson process, involving only two parameters, expressed as a Mittag-Leffler (ML) function. Here, we also propose a combo of Fowler-Nordheim (FN) and Poole-Frenkel (PF) models for leakage currents, based on tunnel effect transport through the oxide. It gives the leakage current on a medium-to-long scale of time while the ML model can possibly take into account a shorter time step. The perspective is to find a relationship between these different models, used in various fields, to propose a generic model of phenomena involving leakage in complex and porous materials at different scales of time and space

Fiabilité des Mémoires Non-Volatiles de type Flash en architectures NOR et NAND

Cette thèse étudie divers aspects de la fiabilité des mémoires, notamment les tests en endurance et les tenues en rétention sur des mémoires Flash, en architectures NOR et NAND. Nous abordons différentes méthodes de programmation existantes dans la littérature, à savoir l'utilisation de signaux très courts et un algorithme de programmation intelligent, que nous avons appliquées sur nos cellules mémoires afin de réduire la dégradation qu'elles subissent lors des phases successives de programmation /effacement. Les améliorations observées n'étant pas significatives, nous n'avons pas choisi d'utiliser de tels signaux dans la suite de notre étude. Nous présentons également une théorie des signaux optimisés qui n'a pas été approfondie ici mais que nous avons étudiée dans une étude préalable à cette thèse. Nous présentons ensuite une modélisation des pertes de charges en rétention à partir d'équations simples de types Fowler-Nordheim et Poole-Frenkel qui se superposent et respectivement prépondérantes à des temps de rétention élevés (t>200h) et courts (t<200h). Nous proposons enfin une étude des perturbations intervenant dans une matrice mémoire, à la fois du point de vue des tensions électriques appliquées sur les cellules mais aussi du point de vue des capacités de couplages parasites. Nous avons dans un premier temps évalué les valeurs de perturbation de grille sur des cellules mémoires Flash en architecture NOR puis NAND avant de traiter des capacités parasites entre cellules dans une matrice. Nous avons été amenés à étudier ces capacités dans la cadre de l'étude des dégradations excessives des cellules inhibées lors de tests en endurance pour certaines conditions process non-optimisées. Nous avons pour cela développé une simulation TCAD bidimensionnelle à partir des étapes process réelles que nous avons ensuite calibrée sur des mesures sur silicium. Enfin cette simulation a été complétée par une prise en compte des capacités parasites de couplage, extraites sur une simulation tridimensionnelle d'une matrice 3x3 de cellules mémoires. Les valeurs de ces capacités ont été validées par des mesures sur des structures de test spécifiques et par calcul géométrique. Notre simulation bidimensionnelle émule donc un comportement tridimensionnel tout en restant dans une rapidité de calcul liée à une simulation 2D. Nous avons ainsi pu développer des simulations électriques permettant de visualiser le phénomène d'inhibition des cellules, tout au long de l'application des diverses polarisations sur la structure

Fiabilité des mémoires non-volatiles de type flash en architectures NOR et NAND

AIX-MARSEILLE1-Inst.Médit.tech (130552107) / SudocSudocFranceF

A global modeling approach of the leakage phenomena in dielectrics

International audienceThanks to its low noise level, the LSBB environment provides particular environment to carry out high quality electrical characterizations. In this paper, we propose a complete modeling approach of the experimental results from our experimental microelectronic setup. The tested device is a Metal Oxide Semiconductor (MOS) floating gate capacitor which can be found in electrostatic non volatile memories such as Flash. The main idea is to characterize and model the leakage current through the tunnel oxide. We proposed, in a previous work, a model for charge loss considering a fractional Poisson process, involving only two parameters, expressed as a Mittag-Leffler (ML) function. Here, we also propose a combo of Fowler-Nordheim (FN) and Poole-Frenkel (PF) models for leakage currents, based on tunnel effect transport through the oxide. It gives the leakage current on a medium-to-long scale of time while the ML model can possibly take into account a shorter time step. The perspective is to find a relationship between these different models, used in various fields, to propose a generic model of phenomena involving leakage in complex and porous materials at different scales of time and space

Determination of physical properties of semiconductor-oxide-semiconductor structures using a new fast gate current measurement protocol.

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Experimental setup for non-destructive measurement of tunneling currents in semiconductor devices

International audienceA new experimental setup used to perform non-destructive measurement of electrical quantities on semiconductor devices is described in this paper. The particular case of tunneling current measurement in n-type semiconductor–oxide–semiconductor (SOS) capacitors, whose dielectrics play a crucial role in non-volatile memories, has been investigated. When the gates of such devices are polarized with a sufficient bias voltage while the other terminals are grounded, tunnel conduction of electrons through the thin oxide layer is allowed. Typical tunneling current measurements obtained with this advanced setup are presented and compared to the results yielded by older standard experimental protocols. An application to the experimental observation of the temperature dependence of the tunneling current is proposed. Conclusions about the benefits of this kind of electrical measurements are then drawn

True random number generation exploiting SET voltage variability in resistive RAM memory arrays

International audienceA novel True Random Number Generator circuit fabricated in a 130nm HfO2-based resistive RAM process is presented. The generation of the random bit stream is based on a specific programming sequence applied to a dedicated memory array. In the proposed programming scheme, the voltage applied to the cells of the memory array is fixed at the median SET voltage of the distribution, to program only a subset of the memory array, resulting in a stochastic distribution of cell resistance values. Some cells are switched in a low resistive state, while the remaining cells maintain their initial high resistance state. Resistance values are next converted into a bit stream and confronted to National Institute of Standards and Technology (NIST) test benchmarks. The generated random bit stream has successfully passed eleven NIST tests out of fifteen without any post-processing

Effects of Lightly Doped Drain and Channel Doping Variations on Flash Memory Performances and Reliability

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