A study of 4-level DC-DC boost inverter with passive, component reduction consideration

This study is to analyze design principles of boost inductor and capacitor used in the 4-level DC-DC boost converter to realize size reduction of passive component referring to their attributes. The important feature of this circuit is that most of the boost-up energy is transferred from the capacitor-clamped to the output side which the small inductance can be used at the input side. The inductance of the boost inductor is designed by referring the inductor current ripple. On the other hand, the capacitance of the capacitor-clamped is designed by considering voltage stress on semiconductor devices and also the used switching frequency. Besides that, according to the design specifications, the required inductance in 4-level DC-DC boost converter is decreased compared to a conventional conventional DC-DC boost converter. Meanwhile, voltage stress on semiconductor device is depending on the maximum voltage ripple of the capacitor-clamped. A 50 W 4-level DC-DC boost converter prototype has been constructed. The results show that the inductor current ripple was 1.15 A when the inductors, 1 mH and 0.11 mH were used in the conventional and 4-level DC-DC boost converters, respectively. Thus, based on the experimental results, it shows that the reduction of passive components by referring to their attributes in 4-level DC-DC boost converter is achieved. Moreover, the decreasing of voltage stress on the semiconductor devices is an advantage for the selection of low ON-resistance of the devices which will contribute to the reduction of the semiconductor conduction loss. The integration result of boost converter and H-bridge inverter is also shown

A Study on 3-phase Interleaved DC-DC Boost Converter Structure and Operation for Input Current Stress Reduction

This paper analyses a 3-phase interleaved DC-DC boost converter for the conversion of low input voltage with high input current to higher DC output voltage. The operation of the 3-phase interleaved DC-DC boost converter with multi-parallel of boost converters is controlled by interleaved of switching signals with 120 degrees phase-shifted. Therefore, with this circuit configuraion, high input current is evenly shared among the parallel units and consequently the current stress is reduced on the circuit and semiconductor devices and contributes reduction of overall losses. The simulation and hardware results show that the current stress and the semiconductor conduction losses were reduced approximately 33% and 32%, respectively in the 3-phase interleaved DC-DC boost converter compared to the conventional DC-DC boost converters. Furthermore, the use of interleaving technique with continuous conduction mode on DC-DC boost converters is reducing input current and output voltage ripples to increase reliability and efficiency of boost converters

Modular Multilevel DC-DC Boost Converter for High Voltage Gain Achievement with Reduction of Current and Voltage Stresses

  This paper presents a modular multilevel DC-DC boost converter for high voltage gain achievement with reduction of current and voltage stresses. Normally, conventional DC-DC boost converter (CDBC) has low voltage gain capability, higher current and voltage stresses which lead to high conduction loss of the semiconductor devices due to the circuit structure limitation. Therefore, 4-level synchronous modular multilevel DC-DC converter (SMMC) with Marx topology adaptation is considered to improve the limitation circuit structure of CDBC. Besides, the 4-level SMMC have high voltage gain achievement, it also has lower current and voltage stresses features. A 145 W and 48 V input voltage of 4-level SMMC has been designed and experimentally verified where the result is compared with CDBC. The results show that the CDBC required 0.76 of duty cycle while 4-level SMMC only require 0.5 duty cycle to achieve 200 V output voltage, respectively. Additionally, the current stress decreases by 75% on input inductor and 50% reduction from voltage stress of switching as compared to the CDBC. Consequently, the selection rating for the components can be decreased and higher efficiency can be obtained for the 4-level SMMC as compared to the CDBC

A highly miniaturized Ultra-Wideband antenna with a triple-band Notch for wearable applications

In this paper, a compact UWB antenna with a triple-band notch for wearable applications is designed andsimulated for Ultra-Wideband (UWB) applications with theoperating frequency from 3.1GHz to 10.6GHz. The antennacan be used for UWB applications, while at the same time, isable to reject the narrowbands namely, WiMAX (3.2GHz to3.6GHz), C-band (3.7GHz to 4.2GHz) and WLAN (5.15GHz to 5.35GHz). Two slots are introduced on the radiatingpatch of the antenna to notch the three narrowbands,instead of three slots to notch each narrowband. Theantenna is designed on a semi-flexible Rogers DuroidRO3003TM substrate. The final outcomes indicate that theantenna can operate over the UWB frequency from 3.09GHz to 11.09GHz. The antenna is able to notch the WiMAXand C-bands with a frequency range from 3.16GHz to 4.20GHz and the WLAN band with a frequency range from 5.14GHz to 5.34GHz. The performance of the antenna inbending condition is also examined with the antenna bentover a varying diameter of vacuum cylinder starting from50mm, 80mm and 100mm. It is shown from the reflectioncoefficient of each diameter that the performance of theantenna is not affected by bending and thus, is particularlyuseful to be worn on body for wearable applications, otherthan its compact size of 19mm×14mm. The SAR resultsobtained shows that the antenna obeys the guidelines for1mW of input power

Purpose-built test rig for gas insulation breakdown tests under lightning impulse

A new test rig has been developed specifically for gas research work, which includes a pressure chamber, control measures, and a recovery system of the gas. The air-tight pressure chamber was designed and tested to withstand pressures of up to 5 bar (abs). Through help from a reliable sealing gland, wires were passed through the pressurized gas inside the vessel to the outside to provide a means of controlling the gap length of the electrodes, without the need of removing the gas. Other control measures include humidity, temperature, and pressure readings. The humidity and temperature are read wirelessly and from the readings, the necessary atmospheric corrections can be made according to standards. Safety measures are equally important and were achieved by using a pressure relief valve. The valve is set to release the gas at 6 bar. A recovery system of the gas mixture was used so that after each test, the gas was properly stored in cylinder bottles and not being released into the atmosphere. As it is important to study the `deteriorated' gas for future works, this recovery process provided a means of obtaining the deteriorated gas to be investigated. From initial tests on air breakdown, it was found that U50 increases with pressure. Rod-plane configuration provides lowest U50 values due to its electrode geometry, followed by R12-plane and plane-plane configurations

Symmetrical and Asymmetrical Multilevel Inverter Structures with Reduced Number of Switching Devices

The purpose of this study is to analyze the operation and design of symmetrical and asymmetrical multilevel inverter structures with reduced number of switching devices. In this study, the term of conventional inverter is defined as a single cascaded inverter. Specifically, the inverter operates in three complete loops and only produces 2-level and 3-level of output voltages. Usually, cascaded structure suffers from the high total harmonic distortion. Thus, by considering multilevel structure of inverter, low total harmonic distortion reduction and voltage stress reduction on switching devices can be archived. Sinusoidal pulse width modulation and modified square pulse width modulation are used as modulation techniques in switching schemes of the designed multilevel inverters. The findings indicate that, the designed multilevel structure cause low total harmonics distortion at the output voltage. Furthermore, the asymmetrical structure is producing the same output voltage levels with reduced number of switching devices compared to the symmetrical structure is experimentally confirmed. The findings show that the total harmonic distortion for 7-level (symmetrical) and 9-level (asymmetrical) are 16.45% and 15.22%, respectively