78 research outputs found
Timing Analysis for DAG-based and GFP Scheduled Tasks
Modern embedded systems have made the transition from single-core to
multi-core architectures, providing performance improvement via parallelism
rather than higher clock frequencies. DAGs are considered among the most
generic task models in the real-time domain and are well suited to exploit this
parallelism. In this paper we provide a schedulability test using response-time
analysis exploiting exploring and bounding the self interference of a DAG task.
Additionally we bound the interference a high priority task has on lower
priority ones
Runtime CRPD management for rate-based scheduling
Temporal isolation is an increasingly relevant con-
cern in particular for ARINC-351 and virtualisation-
based systems. Traditional approaches like the rate-
based scheduling framework RBED do not take into
account the impact of preemptions in terms of loss of
working set in the acceleration hardware (e.g. caches).
While some improvements have been suggested in the
literature, they are overly heavy in the presence of small
high-priority tasks such as interrupt service routines.
Within this paper we propose an approach enabling
adaptive assessment of this preemption delay in a tem-
poral isolation framework with special consideration of
capabilities and limitations of the approach.This work was supported by the Portuguese Science
and Technology Foundation (FCT) (CISTER FCT-608) and
ARTEMIS-JU (RECOMP project ARTEMIS/0202/2009
Real-Time Application Mapping for Many-Cores Using a Limited Migrative Model
Many-core platforms are an emerging technology in the real-time embedded domain. These devices offer various options for power savings, cost reductions and contribute to the overall system flexibility, however, issues such as unpredictability, scalability and analysis pessimism are serious challenges to their integration into the aforementioned area. The focus of this work is on many-core platforms using a limited migrative model (LMM). LMM is an approach based on the fundamental concepts of the multi-kernel paradigm, which is a promising step towards scalable and predictable many-cores. In this work, we formulate the problem of real-time application mapping on a many-core platform using LMM, and propose a three-stage method to solve it. An extended version of the existing analysis is used to assure that derived mappings (i) guarantee the fulfilment of timing constraints posed on worst-case communication delays of individual applications, and (ii) provide an environment to perform load balancing for e.g. energy/thermal management, fault tolerance and/or performance reasons
The roman conquered by delay: reducing the number of preemptions using sleep states
Sleep-states are emerging as a first-class design choice
in energy minimization. A side effect of this is that the release
behavior of the system is affected and subsequently the
preemption relations between tasks. In a first step we have
investigated how the behavior in terms of number of preemptions
of tasks in the system is changed at runtime, using
an existing procrastination approach, which utilizes sleepstates
for energy savings purposes. Our solution resulted
in substantial savings of preemptions and we expect from
even higher yields for alternative energy saving algorithms.
This work is intended to form the base of future research,
which aims to bound the number of preemptions at analysis
time and subsequently how this may be employed in the
analysis to reduced the amount of system utilization, which
is reserved to account for the preemption delay
Device power management for real-time embedded systems
A large part of power dissipation in a system is generated by I/O devices. Increasingly these devices provide power
saving mechanisms to inter alia enhance battery life. While I/O device scheduling has been studied in the past for
realtime systems, the use of energy resources by these scheduling algorithms may be improved. These approaches are
crafted considering a huge overhead of device transition. The technology enhancement has allowed the hardware
vendors to reduce the device transition overhead and energy consumption. We propose an intra-task device scheduling
algorithm for real time systems that allows to shut-down devices while ensuring the system schedulability. Our results
show an energy gain of up to 90% in the best case when compared to the state-of-the-art
Energy-conscious tasks partitioning onto a heterogeneous multi-core platform
Modern multicore processors for the embedded market
are often heterogeneous in nature. One feature often available
are multiple sleep states with varying transition cost for entering
and leaving said sleep states. This research effort explores the
energy efficient task-mapping on such a heterogeneous multicore
platform to reduce overall energy consumption of the system.
This is performed in the context of a partitioned scheduling
approach and a very realistic power model, which improves
over some of the simplifying assumptions often made in the
state-of-the-art. The developed heuristic consists of two phases,
in the first phase, tasks are allocated to minimise their active
energy consumption, while the second phase trades off a higher
active energy consumption for an increased ability to exploit
savings through more efficient sleep states. Extensive simulations
demonstrate the effectiveness of the approach
Slow down or race to halt: towards managing complexity of real-time energy management decisions
Existing work in the context of energy management for real-time systems
often ignores the substantial cost of making DVFS and sleep state decisions
in terms of time and energy and/or assume very simple models. Within this paper
we attempt to explore the parameter space for such decisions and possible
constraints faced
Measurements or Static Analysis or Both?
To date, measurement-based WCET analysis and
static analysis have largely been seen as being at
odds with each other. We argue that instead they
should be considered complementary, and that the
combination of both represents a promising approach
that provides benefits over either individual
approach. In this paper we discuss in some
detail how we aim to improve on our probabilistic
measurement-based technique by adding static
cache analysis. Specifically we are planning to
make use of recent advances within the functional
languages research community. The objective of
this paper is not to present finished or almost finished
work. Instead we hope to trigger discussion
and solicit feedback from the community in order
to avoid pitfalls experienced by others and to help
focus our research
Comparing the schedulers and power saving strategies with SPARTS
We have developed SPARTS, a simulator of a
generic embedded real-time device. It is designed to be extensible
to accommodate different task properties, scheduling algorithms
and/or hardware models for the wide variety of applications.
SPARTS was developed to help the community investigate the
behaviour of the real-time embedded systems and to quantify
the associated constraints/overheads
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