Terahertz rectifyier for integrated image detector

We present a new CMOS compatible direct conversion terahertz detector operating at room temperature. The rectenna consists in a truncated conical helix extruded from a planar spiral and connected to a nanometric metallic whisker at one of its edges. The whisker reaches the semiconductor substrate that constitutes the antenna ground plane. The rectifying device can be obtained introducing some simple modifications of the charge storage well in conventional CMOS APS devices, making the proposed solution easy to integrate with existing imaging systems. No need of scaling toward very scaled and costly technological node is required, since the CMOS only provides the necessary integrated readout electronics. On-wafer measurements of RF characteristics of the designed rectifying junction are reported and discussed

CMOS-Compatible Room-Temperature Rectifier Toward Terahertz Radiation Detection

In this paper, we present a new rectifying device, compatible with the technology of CMOS image sensors, suitable for implementing a direct-conversion detector operating at room temperature for operation at up to terahertz frequencies. The rectifying device can be obtained by introducing some simple modifications of the charge-storage well in conventional CMOS integrated circuits, making the proposed solution easy to integrate with the existing imaging systems. The rectifying device is combined with the different elements of the detector, composed of a 3D high-performance antenna and a charge-storage well. In particular, its position just below the edge of the 3D antenna takes maximum advantage of the high electric field concentrated by the antenna itself. In addition, the proposed structure ensures the integrity of the charge-storage well of the detector. In the structure, it is not necessary to use very scaled and costly technological nodes, since the CMOS transistor only provides the necessary integrated readout electronics. On-wafer measurements of RF characteristics of the designed junction are reported and discussed. The overall performances of the entire detector in terms of noise equivalent power (NEP) are evaluated by combining low-frequency measurements of the rectifier with numerical simulations of the 3D antenna and the semiconductor structure at 1 THz, allowing prediction of the achievable NEP

The polymorphism L412F in TLR3 inhibits autophagy and is a marker of severe COVID-19 in males

The polymorphism L412F in TLR3 has been associated with several infectious diseases. However, the mechanism underlying this association is still unexplored. Here, we show that the L412F polymorphism in TLR3 is a marker of severity in COVID-19. This association increases in the sub-cohort of males. Impaired macroautophagy/autophagy and reduced TNF/TNFα production was demonstrated in HEK293 cells transfected with TLR3L412F-encoding plasmid and stimulated with specific agonist poly(I:C). A statistically significant reduced survival at 28 days was shown in L412F COVID-19 patients treated with the autophagy-inhibitor hydroxychloroquine (p = 0.038). An increased frequency of autoimmune disorders such as co-morbidity was found in L412F COVID-19 males with specific class II HLA haplotypes prone to autoantigen presentation. Our analyses indicate that L412F polymorphism makes males at risk of severe COVID-19 and provides a rationale for reinterpreting clinical trials considering autophagy pathways. Abbreviations: AP: autophagosome; AUC: area under the curve; BafA1: bafilomycin A1; COVID-19: coronavirus disease-2019; HCQ: hydroxychloroquine; RAP: rapamycin; ROC: receiver operating characteristic; SARS-CoV-2: severe acute respiratory syndrome coronavirus 2; TLR: toll like receptor; TNF/TNF-α: tumor necrosis factor

Common, low-frequency, rare, and ultra-rare coding variants contribute to COVID-19 severity

The combined impact of common and rare exonic variants in COVID-19 host genetics is currently insufficiently understood. Here, common and rare variants from whole-exome sequencing data of about 4000 SARS-CoV-2-positive individuals were used to define an interpretable machine-learning model for predicting COVID-19 severity. First, variants were converted into separate sets of Boolean features, depending on the absence or the presence of variants in each gene. An ensemble of LASSO logistic regression models was used to identify the most informative Boolean features with respect to the genetic bases of severity. The Boolean features selected by these logistic models were combined into an Integrated PolyGenic Score that offers a synthetic and interpretable index for describing the contribution of host genetics in COVID-19 severity, as demonstrated through testing in several independent cohorts. Selected features belong to ultra-rare, rare, low-frequency, and common variants, including those in linkage disequilibrium with known GWAS loci. Noteworthily, around one quarter of the selected genes are sex-specific. Pathway analysis of the selected genes associated with COVID-19 severity reflected the multi-organ nature of the disease. The proposed model might provide useful information for developing diagnostics and therapeutics, while also being able to guide bedside disease management. © 2021, The Author(s)

A robust start-up Class-C CMOS VCO based on common mode low frequency feedback loop

Many Class-C CMOS VCOs have been introduced in the last decade claiming to achieve improved phase noise performance and power efficiency with apparently no tradeoff, however only in the past two years implementation efforts have been focused on stability related issues of such oscillator architectures. In fact, oscillators exploiting time-varying bias techniques may present several stability points and for this reason dedicated start-up circuits are needed to reach the desired periodic steady state regime. In this paper we introduce a novel stabilization technique for a CMOS VCO polarized in Class-C via a common mode feedback loop with the aim to ensure a robust start-up with no significant phase-noise and power efficiency degradation. The VCO core is based on a crossed pair of NMOS devices refilling a symmetric resonator with a center tapered inductor and biased by a top PMOS current generator. The proposed Class-C VCO is implemented in a RF 55nm CMOS technology and is tunable over the frequency band 6.6-8.2 GHz with average phase noise lower than -127 dBc/Hz @ 1 MHz offset and mean power consumption of 18mW, for a state-of-the-art figure-of-merit of -190 dBc/Hz @ 1 MHz offset. © 2014 IEEE

Floquet eigenvectors theory of pulsed bias phase and quadrature harmonic oscillators

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Microwave sensing of nanostructured semiconductor surfaces

In this paper, we present a method for the characterization of the lifetime of photoinduced carriers in semiconductor nanostructures based on the interaction of the photocarriers with the evanescent electric field of a microwave, propagating in a coplanar waveguide. The limited spatial extension of the evanescent field ensures that only a defined portion of material is analyzed. The nanostructures are illuminated by pulses of ultraviolet light which ensures that absorption and photogeneration occur mainly within the semiconductor nanostructure. Absorption due to photogenerated carriers produces weak variations of the power of microwaves travelling along the coplanar structure. Time variations of transmitted power through the waveguide thus follow the time variations of photogenerated charges. The technique is completely contactless, and ensures fast and non-destructive test capability. The measurement was applied for monitoring of lifetime of photogenerated carriers in macroporous silicon, proving to be strongly effective. (C) 2014 AIP Publishing LLC

Phase and quadrature pulsed bias LC CMOS VCO

Pulsed bias is an attempt to improve the performance of oscillators in integrated circuits as a result of architectural innovation. Given the relatively low value of resonator quality factor achievable on-chip, for a specified bias voltage level, pulsed bias may result in a lower power consumption and in an improvement of the spectral purity of the oscillation. The main drawback of this approach is the need to introduce a certain time delay in order to properly position pulses with respect to oscillation waveform. Delay accumulation requires further energy dissipation and introduce additional jitter. In this paper we present a new architecture capable to avoid unnecessary delay, based on the idea to apply the pulsed bias approach to a quadrature oscillator. A first circuit-level implementation of this concept is presented with simulation results