Nanowire Transistors and RF Circuits for Low-Power Applications

The background of this thesis is related to the steadily increasing demand of higher bandwidth and lower power consumption for transmitting data. The work aims at demonstrating how new types of structures, at the nanoscale, combined with what is referred to as exotic materials, can help benefit in electronics by lowering the consumed power, possibly by an order of magnitude, compared to the industry standard, silicon (Si), used today. Nanowires are semiconductor rods, with two dimensions at the nanoscale, which can be either grown with a bottom-up technique, or etched out with a top-down approach. The research interest concerning nanowires has gradually increasing for over two decades. Today, few have doubts that nanowires represent an attractive alternative, as scaling of planar structures has reached fundamental limits. With the enhanced electrostatics of a surrounding gate, nanowires offer the possibility of continued miniaturization, giving semiconductors a prolonged window of performance improvements. As a material choice, compound semiconductors with elements from group III and V (III-Vs), such as indium arsenide (InAs), have the possibility to dramatically decrease power consumption. The reason is the inherent electron transport properties of III-Vs, where an electron can travel, in the order of, 10 times faster than in Si. In the projected future, inclusion of III-Vs, as an extension to the Si-CMOS platform, seems almost inevitable, with many of the largest electronics manufacturing companies showing great interest. To investigate the technology potential, we have fabricated InAs nanowire metal-oxide-semiconductor field effect transistors (NW-FETs). The performance has been evaluated measuring both RF and DC characteristics. The best devices show a transconductance of 1.36 mS/µm (a device with a single nanowire, normalized to the nanowire circumference) and a maximum unilateral power gain at 57 GHz (for a device with several parallel nanowires), both values at a drive voltage of 0.5 V. The performance metrics are found to be limited by the capacitive load of the contact pads as well as the resistance in the non-gated segments of the nanowires. Using computer models, we have also been able to extract intrinsic transport properties, quantifying the velocity of charge carrier injection, which is the limiting property of semi-ballistic and ballistic devices. The value for our 45-nm-in-diameter nanowires, with 200 nm channel length, is determined to 1.7∙107 cm/s, comparable to other state-of-the-art devices at the same channel length. To demonstrate a higher level of functionality, we have connected several NW-FETs in a circuit. The fabricated circuit is a single balanced differential direct conversion mixer and is composed of three stages; transconductance, mixing, and transimpedance. The basic idea of the mixer circuit is that an information signal can either be extracted from or inserted into a carrier wave at a higher frequency than the information wave itself. It is the relative size of the first and the third stage that accounts for the circuit conversion gain. Measured circuits show a voltage conversion gain of 6 dB and a 3-dB bandwidth of 2 GHz. A conversion mixer is a vital component when building a transceiver, like those found in a cellphone and any other type of radio signal transmitting device. For all types of signals, noise imposes a fundamental limitation on the minimal, distinguishable amplitude. As transistors are scaled down, fewer carriers are involved in charge transport, and the impact of frequency dependent low-frequency noise gets relatively larger. Aiming towards low power applications, it is thus of importance to minimize the amount of transistor generated noise. Included in the thesis are studies of the level and origin of low-frequency 1/f-noise generated in NW-FETs. The measured noise spectral density is comparable to other non-planar devices, including those fabricated in Si. The data suggest that the level of generated noise can be substantially lowered by improving the high-k dielectric film quality and the channel interface. One significant discovery is that the part of the noise originating from the bulk nanowire, identified as mobility fluctuations, is comparably much lower than the measured noise level related to the nanowire surface. This result is promising as mobility fluctuations set the lower limit of what is achievable within a material system

1/f-noise in Vertical InAs Nanowire Transistors

The material quality at high-k interfaces are a major concern for FET devices. We study the effect on two types of InAs nanowire (NW) transistors and compare their characteristics. It is found that by introducing an inner layer of Al2O3 at the high-kappa interface, the low frequency noise (LFN) performance regarding gate voltage noise spectral density, S-Vg, is improved by one order of magnitude per unit gate area

Lead-Time Effect Comparison of Additive Manufacturing with Conventional Alternatives

This single case study used value stream mapping as input data to analyse alternatives for production of quenching tools in an on-site tool department of an automotive manufacturer. The existing manufacturing organised as a functional workshop was compared to the alternatives, adding an additive manufacturing cell or a conventional automated cell, with regards to lead-Time and needed process changes. The results indicate that lead-Time savings should not be the only reason for considering additive manufacturing. When it is beneficial for design and product functionality improvements, however, lead time improvements may give a contribution to the business case

Low-frequency noise in vertical InAs nanowire FETs

This letter presents dc characteristics and low-frequency noise (LFN) measurements on single vertical InAs nanowire MOSFETs with 35-nm gate length and HfO2 high-kappa dielectric. The average normalized transconductance for three devices is 0.16 S/mm, with a subthreshold slope of 130 mV/decade. At 10 Hz, the normalized noise power S-I/I-d(2) measures 7.3 x 10(-7) Hz(-1). Moreover, the material-dependent Hooge's parameter at room temperature is estimated to be 4.2 x 10(-3)

The Effect of Deposition Conditions on Heterointerface-Driven Band Alignment and Resistive Switching Properties

Titanium nitride and hafnium oxide stack have been widely used in various resistive memory elements since the materials are complementary-metal-oxide-semiconductor compatible. The understanding of the interface properties between the electrode and the oxide is important in designing the memory behavior. To bridge this understanding, HfOx grown using plasma enhanced atomic layer deposition (PEALD) and thermal atomic layer deposition (TALD) are compared, in terms of band alignment and electrical performances in the HfOx/PEALD TiN stacks. X-ray photoelectron spectroscopy reveals a thicker interfacial TiO2 layer in the PEALD HfOx/TiN stack whose interface resembles more to the PEALD HfOx/TiO2 interface (conduction band offset ΔEC = 1.63 eV), whereas the TALD HfOx stack interface resembles more to the TALD HfOx/TiN interface (ΔEC = 2.22 eV). The increase in the forming voltage and the early onset of reverse filament formation (RFF) in the I–V measurements for the PEALD HfOx stack confirms the presence of the thicker interfacial layer; the early onset of RFF is likely related to a smaller ΔEC. The findings show the importance of understanding the intricate details of the material stack, where ΔEC difference and the presence of a thicker TiO2 interfacial layer due to different deposition procedures affect the device performance