Vessel-level productivity in Commonwealth fisheries

The total factor productivity of the Commonwealth Trawl Sector of the Southern and Eastern Scalefish and Shark Fishery is estimated for the period 1996–97 to 2008–09 using vessel-level data and a traditional approach that captures the production decisions of fishers. The paper develops a replicable methodology and calculates benchmark productivity estimates by which future estimates for other Commonwealth fisheries can be evaluated. Productivity estimates presented in this paper are based on vessel-level financial and catch data collected by ABARES in its annual survey of the fishery and the application of the Fisher index method. The analysis of trends in productivity offers important new information to decision-makers. Changes in the way in which fishers organise the transformation of inputs into outputs have a direct impact on firm-level economic performance. Changes in productivity at the vessel level illustrate the response of the fleet to policy settings in the fishery and, more broadly, to environmental factors. This is of particular value for fishery managers when they consider policy instruments—such as fish stocks, technology and fleet structure—that might affect the drivers of productivity growth in fisheries.Agribusiness, Resource /Energy Economics and Policy,

WMTrace : a lightweight memory allocation tracker and analysis framework

The diverging gap between processor and memory performance has been a well discussed aspect of computer architecture literature for some years. The use of multi-core processor designs has, however, brought new problems to the design of memory architectures - increased core density without matched improvement in memory capacity is reduc- ing the available memory per parallel process. Multiple cores accessing memory simultaneously degrades performance as a result of resource con- tention for memory channels and physical DIMMs. These issues combine to ensure that memory remains an on-going challenge in the design of parallel algorithms which scale. In this paper we present WMTrace, a lightweight tool to trace and analyse memory allocation events in parallel applications. This tool is able to dynamically link to pre-existing application binaries requiring no source code modification or recompilation. A post-execution analysis stage enables in-depth analysis of traces to be performed allowing memory allocations to be analysed by time, size or function. The second half of this paper features a case study in which we apply WMTrace to five parallel scientific applications and benchmarks, demonstrating its effectiveness at recording high-water mark memory consumption as well as memory use per-function over time. An in-depth analysis is provided for an unstructured mesh benchmark which reveals significant memory allocation imbalance across its participating processes

Design Practice in the UK Car Industry: How Coventry University is Addressing the Needs

This paper considers the needs of the UK car industry and identifies specific situations that have serious implications upon design practice. The response at Coventry University to these needs is discussed and our PAKTS model for Design Education introduced