Digital Signal Processing and Mixed Signal Control of Receiver Circuitry for Large-Scale Particle Detectors

The Jiangmen Underground Neutrino Observatory (JUNO) is a multi-purpose underground experiment based on a 20,000 ton liquid scintillator with the primary objective of determining the neutrino mass hierarchy. The signal detection is performed by photomultipliers PMT and integrated readout electronics. The central component for the digitization process is a receiver chip with a low power analog to digital conversion unit of large dynamic range. In order to efficiently utilize the conversion unit’s dynamic range, a custom data processor and a regulation circuit were included in the chip. In this thesis, the design, development and prototype measurements of the data processing unit and a regulation circuit included in the analog to digital conversion unit are presented. The processor analyzes the data and performsd ata reduction resulting in efficient utilization of output bandwidth. Based on the systemand event information transmitted by the processor along with the data, successful signal reconstruction was carried out. The regulation circuit reduces the noise level thereby increasing the effective number of bits available for the signal. The complexity of the PMT installation poses difficulty to replace faulty electronics during runtime of the experiment. A design for test structure included in the receiver chip with the intention to extract defect free electronics during testing of the mass-produced chips is also described. The introduction of test structures in the design successfully increased the overall test coverage. Finally, the insights from the developed model of the receiver chain are presented

A Highly-Integrated Receiver Chip for the JUNO Experiment

The Jiangmen Underground Observatory (JUNO) is a planned neutrino experiment currently being built in Jiangmen, China, with a baseline of 53 km to two nuclear reactors and an expected data taking start in 2020. It is a multi-purpose detector with its main goal to determine the neutrino mass hierarchy. The neutrinos will be measured with a detector based on a sphere filled with 20 kton of liquid scintillator. The light emitted from the scintillator is observed by ~18 000 large (20 inch) photomultipliers (PMTs) and ~34 000 small (3 inch) PMTs. The former are designed as intelligent units with their control and readout embedded into the casing. To digitize the signals with a sampling rate of 1 Gsamples/s, a highly-integrated solution is under development – called Vulcan – that includes the analog to digital converter (ADC) and the analog frontend without the need for external components. After digitization, the digital part of Vulcan prepares the data stream for further data management in an FPGA. An overview of the concept and design of Vulcan will be presented along with measurements of the first prototype

Methodology for Power-Aware Coherent Receiver Design

We describe a methodology to design and evaluate DSP hardware for a coherent receiver. Important parameters that can be assessed include DSP power consumption and chip area

Modeling and Simulation of Digital Phase-Locked Loop in Simulink

This paper presents a high-level model for a digital phase-locked loop implemented in Simulink. This modeling enables the flexible and fast estimation of the design behavior and parameters before transistor-level implementation. The design includes a digital controlled oscillator that is defined using a linear s-domain model. Furthermore, the design of a time-to-digital converter based on oversampling and noise shaping is introduced to increase the effective resolution of the block. The simulation results of locking process, stability and phase noise verify the functionality of the model

A Highly Integrated Receiver Chip with an Automatic Baseline Regulation for JUNO

This paper describes the data processing unit and an automatic baseline regulation of a highly integrated readout chip (Vulcan) for JUNO. The chip collects data continuously at 1 Gsamples/sec. The Primary data processing which is performed in the integrated circuit can aid to reduce the memory and data processing efforts in the subsequent stages. In addition, a baseline regulator compensating a shift in the baseline is described

SQuBiC1: An integrated control chip for semiconductor qubits

The Central Institute for Electronic Systems at Forschungszentrum Jülich develops, designs and tests scalable solutions for the control and readout of qubits to be used in future quantum computers. The focus lies on highly integrated system-on-chip (SoC) solutions leveraging state-of-the-art commercial semiconductor technologies.We are working according to the V-model of engineering to approach system solutions in a top-down design and bottom-up implementation. As part of the bottom-up implementation, we designed and layouted a first test chip in a commercial 65nm CMOS process . The chip contains all infrastructure needed to control a GaAs semiconductor qubit. It features a DC-digital-to-analog converter (DC-DAC) that generates the tuning voltages in the range of 0V to +1V to bring the qubit into the operation point. The pulse DAC, running at 250MHz, generates pulses with ± 4mV amplitude to generate gate sequences for operating the qubit. In this presentation, we will describe the chip architecture in detail and show corresponding simulation results

SQuBiC1: An Integrated Control Chip for Semiconductor Spin Qubits

In most quantum experiments nowadays the control and readout electronics is placed at room temperature. The number of qubits which can be operated with this approach is severely limited by the number of interconnects and the wiring between the qubit operating temperature level and the room temperature level. At the Central Institute for Electronic Systems at the Forschungszentrum Jülich we develop and design scalable solutions for readout and control of qubits for future use in quantum computers. Our approach leverages the advances of state-of-the-art commercial CMOS technologies while operating at deep-cryogenic temperatures close to the actual qubit. We designed and layouted a first chip for concept proof in a commercial 65 nm CMOS process. This chip contains a DC-digital-to-analog converter (DC-DAC), a pulse digital-to-analog converter, a 500 MHz digitally controlled current starved ring oscillator and a 20 GHz LC-oscillator. The DC-DAC is operating in a voltage range between 0 V and 1 V. The pulse DAC operates at a sample rate of 250 MHz and generates pulses in a range of 8 mV. In this presentation the chip architecture will be discussed in detail and corresponding simulation results will be shown