Relação entre qualidade de vida e prevalencia de ideação suicida em pacientes atendidos no programa de transtorno de humor : HCPA

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EFFECT OF THE DISTRIBUTION OF STATES IN AMORPHOUS IN-GA-ZN-O LAYERS ON THE CONDUCTION MECHANISM OF THIN FILM TRANSISTORS ON ITS BASE

Amorphous In-Ga-Zn-O Thin Film Transistors (a-IGZO TFTs) have proven to be an excellent approach for flat panel display drivers using organic light emitting diodes, due to their high mobility and stability compared to other types of TFTs. These characteristics are related to the specifics of the metal-oxygen-metal bonds, which give raise to spatially distributed s orbitals that can overlap between them. The magnitude of the overlap between s orbitals seems to be little sensitive to the presence of the distorted bonds, allowing high values of mobility, even in devices fabricated at room temperature. In this paper, we show the effect of the distribution of states in the a-IGZO layer on the main conduction mechanism of the a-IGZO TFTs, analyzing the behavior with temperature of the drain current.

Analog circuit design using graded-channel silicon-on-insulator nMOSFETs

An extended study of analog circuit design using graded-channel (GC) silicon-on-insulator (SOI) MOSFETs in comparison to conventional fully depleted (1713) transistors is performed. Performances of single-transistor operational transconductance amplifier (OTA) implemented using GC and conventional FD SOI nMOSFETs are compared. Improvements of the DC gain and unity-gain frequency resulting from the extremely reduced output conductance and the increased transconductance in the GC devices are discussed, based on experimental results, establishing design guidelines in order to aim at GC micropower or wide bandwidth OTAs. Two-dimensional simulations are used to analyze the intrinsic-gate capacitances in linear and saturation regions, establishing that GC transistors present almost the same capacitive amount than the conventional FD transistors in a typical analog range of operation. Current mirrors fabricated using GC and conventional MOSFETs are compared. It is demonstrated that GC MOSFETs can provide high precision current mirrors with enhanced output swing. (C) 2002 Elsevier Science Ltd. All rights reserved

Graded-channel fully depleted Silicon-On-Insulator nMOSFET for reducing the parasitic bipolar effects

An extended study of the occurrence of inherent parasitic bipolar effects in conventional and graded-channel fully depleted silicon-on-insulator nMOSFETs is carried out. The graded-channel device is a new asymmetric channel MOSFET, fabricated through a simple process variation. Measurements and two-dimensional simulations are used to demonstrate that the graded-channel device efficiently alleviates the parasitic BJT action, improving the breakdown voltage, by the reduction of impact ionization in the high electric field region. Based on process/device simulation and modeling, multiplication factor and parasitic bipolar gain, which are the responsible parameters for the parasitic BJT action, are investigated separately providing a physical explanation. The abnormal subthreshold slope and hysteresis phenomenon are also studied and compared. (C) 2000 Elsevier Science Ltd. All rights reserved

A physically-based continuous analytical graded-channel SOI nMOSFET model for analog applications

In this work a continuous model for analog simulation of long-channel Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs is presented. The model is based in a series association of two conventional fully-depleted (FD) SOI nMOSFETs with different characteristics, representing each part of the GC nMOSFET channel region. MEDICI numerical bidimensional simulations and experimental results are used to validate the proposed model

An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics

A device based on an asymmetric channel doping profile with the aim of reducing the inherent parasitic bipolar effects in fully depleted silicon-on-insulator (SOI) devices and improving the output characteristics is introduced. Measurements and two-dimensional simulations are used to study the device capabilities and limitations. (C) 1999 The Electrochemical Society. S1099-0062(99)07-087-X. All rights reserved

A physically-based continuous model for graded-channel SOI MOSFET

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Analysis of source-follower buffers implemented with graded-channel SOI nMOSFETs operating at cryogenic temperatures

This work studies the operation of source-follower buffers implemented with standard and graded-channel (GC) fully depleted (FD) SCI nMOSFETs at low temperatures. The analysis is performed by comparing the voltage gain of buffers implemented with GC and standard SOI nMOS transistors considering devices with the same mask channel length and same effective channel length. It is shown that the use of GC devices allows for achieving improved gain in all inversion levels in a wide range of temperatures. In addition, this improvement increases as temperature is reduced. It is shown that GC transistors can provide virtually constant gain, while for standard devices, the gain departs from the maximum value depending on the temperature and inversion level imposed by the bias current and input voltage. Two-dimensional numerical simulations were performed in order to study the reasons for the enhanced gain of GC MOSFETs at low temperatures. (C) 2009 Elsevier Ltd. All rights reserved