Heterogeneous memristive crossbar for in-memory computing

It's been quite a while since scientists are seeking for the ancestor of von Neumann computing architecture. Among the most promising candidates, memristor demonstrates advantageous characteristics, which open new pathways for the exploration of advanced computing paradigms. In this work we propose the design of a novel crossbar geometry, which is heterogeneous in terms of its cross-point devices, allowing for the realization of true in-memory digital logic computations. More specifically, it is a combination of two stacked crossbar arrays with a shared intermediate nanowire layer. The variety of available cross-points types allows the execution of parallel memristive logic computations, where the logic state variable is voltage. Moreover, the utilization of insulating patterns in the crossbar arrays, at the expense of a small area-overhead, permits the simultaneous parallel read/write memory operation of two memory words. Memory/logic operation is determined through control signals driven from the peripheral CMOS-based driving circuitry, which also comprises row/column decoders, tri-state drivers, and summing/ sense amplifiers to allow for the proper programming/reading of the memristive cross-pointsPeer ReviewedPostprint (author's final draft

Experimental demonstration of RRAM-based computational cells for reconfigurable mixed-signal neuro-inspired circuits and systems

Modern electronics drive a shift from distributed, cloud and/or mainframe computing towards the ‘edge’. To realise this vision, we need access to hardware technologies that are both energy and scale efficient. During the last decade, the introduction of Resistive Random Access Memory (RRAM), also known as memristors, has fuelled interest in extending conventional circuits’ capabilities. Specifically, their capacity to act as scalable, non-volatile, finely tuneable, electrically programmable resistive elements render them promising candidates for future computer architectures. RRAM technologies have been considered by many as a promising candidate for implementing reconfigurable neuro-inspired circuits and systems capable of processing data in both digital and analogue formats. Presently, there is no extensive study of the behaviour of such circuits when realised physically with real RRAM devices. Hence, there are ample opportunities for developing novel electronic circuits for reconfigurable mixed-signal data processors in silico.This thesis explores the design, implementation and testing of in-silico data processors capable of mapping data from one information domain to another and enabling a mixed-signal data processing. Through this research, I am introducing RRAM-based circuit designs operationally validated through simulations with state-of-art RRAM device model and then practically implemented proof-of-concept designs of these hybrid RRAM-CMOS circuits on hardware. The hardware implementation and testing of low-complexity primitive RRAM-based circuits that can process information in the analogue domain due to the introduction of programmable RRAM devices is the main contributions through this project. In this work, findings are presented regarding the implementation and testing in hardware of a RRAM-based primitive Multiply-Accumulate circuit, RRAM-enhanced Threshold Logic Gate design and as well as larger circuits on these primitive circuits that are easily integrated into RRAM-based In-Memory Computing (IMC) architectures. A primitive RRAM-based MAC circuit is designed and its behaviour exhibited in both simulation (Cadence Virtuoso Spectre) and in hardware. This circuit is used for a proof-of-concept Winner-Take-All systems that showcases 300fJ energy and 1.4ns delay per operation. Additionally, A RRAM-based Threshold Logic Gate is designed and showcased achieving 27.2µW and 0.14ns per operation. Finally, a RRAM-based Wake-Up Circuit is showcased to be feasible using the the aforementioned circuits inside an IMC system

Plane-splitting logic techniques using hybrid CMOS-memristor circuits and systems

An important cornerstone of data processing is the ability to efficiently capture structure in data. This entails treating the input space as a hyperplane that needs partitioning. We argue that several modern electronic systems can be understood as carrying out such partitionings: from standard logic gates to Artificial Neural Networks (ANNs) (see Figure 1). More recently, memristive technologies equipped such systems with the benefit of continuous tuneability directly in hardware, thus rendering these reconfigurable in a power and space efficient manner [1], [2]. Here, we demonstrate several proof-of-concept examples where memristors enable circuits optimised to carry out different flavours of the fundamental task of splitting the hyperplane. These include memristor-based computational modules, such as multiple-threshold ‘L-shape’ (Fig. 1f) and receptive field based classifiers (Fig. 1e), that are presented within the context of a unified perspective, the general principle of ‘splitting a hyperplane’ efficiently. & more ..

Heterogeneous memristive crossbar for in-memory computing

It's been quite a while since scientists are seeking for the ancestor of von Neumann computing architecture. Among the most promising candidates, memristor demonstrates advantageous characteristics, which open new pathways for the exploration of advanced computing paradigms. In this work we propose the design of a novel crossbar geometry, which is heterogeneous in terms of its cross-point devices, allowing for the realization of true in-memory digital logic computations. More specifically, it is a combination of two stacked crossbar arrays with a shared intermediate nanowire layer. The variety of available cross-points types allows the execution of parallel memristive logic computations, where the logic state variable is voltage. Moreover, the utilization of insulating patterns in the crossbar arrays, at the expense of a small area-overhead, permits the simultaneous parallel read/write memory operation of two memory words. Memory/logic operation is determined through control signals driven from the peripheral CMOS-based driving circuitry, which also comprises row/column decoders, tri-state drivers, and summing/ sense amplifiers to allow for the proper programming/reading of the memristive cross-pointsPeer Reviewe

Processing big-data with memristive technologies: splitting the hyperplane efficiently

An important cornerstone of data processing is the ability to efficiently capture structure in data. This entails treating the input space as a hyperplane that needs partitioning. We argue that several modern electronic systems can be understood as carrying out such partitionings: from standard logic gates to Artificial Neural Networks (ANNs). More recently, memristive technologies equipped such systems with the benefit of continuous tunability directly in hardware, thus rendering these reconfigurable in a power and space efficient manner. Here, we demonstrate several proof-of-concept examples where memristors enable circuits optimised to carry out different flavours of the fundamental task of splitting the hyperplane. These include threshold logic and receptive field based classifiers that are presented within the context of a unified perspective

Dataset for PhD Thesis "Experimental Demonstration of RRAM-based Computational Cells for Reconfigurable Mixed-Signal Neuro-Inspired Circuits and Systems"

Dataset for University of Southampton Doctoral Thesis. Title of Thesis: &quot;Experimental Demonstration of RRAM-based Computational Cells for Reconfigurable Mixed-Signal Neuro-Inspired Circuits and Systems&quot;</span

Dataset for &quot;Practical Implementation of Memristor-Based Threshold Logic Gates&quot;

This dataset supports the publication: Georgios Papandroulidakis, Alexander Serb, Ali Khiat, Geoff V. Merrett, Themis Prodromakis Practical Implementation of Memristor-Based Threshold Logic Gates Transactions on Circuits and Systems I: Regular Papers DOI: 10.1109/TCSI.2019.2902475 For more information see the readme file.</span

Practical implementation of memristor-based threshold logic gate

Current advances in emerging memory technologies enable novel and unconventional computing architectures for high-performance and low-power electronic systems, capable of carrying out massively parallel operations at the edge. One emerging technology, ReRAM, also known to belong in the family of memristors (memory resistors), is gathering attention due to its attractive features for logic and in-memory computing; benefits which follow from its technological attributes, such as nanoscale dimensions, low power operation, and multi-state programming. At the same time, design with CMOS is quickly reaching its physical and functional limitations, and further research towards novel logic families, such as Threshold Logic Gates (TLGs) is scoped. In this paper, we introduce a physical implementation of a memristor-based current-mode TLG (MCMTLG) circuit and validate its design and operation through multiple experimental setups. We demonstrate 2-input, 3-input, and 4-input MCMTLG configurations and showcase their reconfiguration capability. This is achieved by varying memristive weights arbitrarily for shaping the classification decision boundary, thus showing promise as an alternative hardware-friendly implementation of Artificial Neural Networks (ANNs). Through the employment of real memristor devices as the equivalent of synaptic weights in TLGs, we are realizing components that can be used towards an in-silico classifier