The FASTER vision for designing dynamically reconfigurable systems

Extending product functionality and lifetime requires constant addition of new features to satisfy the growing customer needs and the evolving market and technology trends. software component adaptivity is straightforward but not enough: recent products include hardware accelerators for reasons of performance and power efficiency that also need to adapt to new requirements. Reconfigurable logic allows the definition of new functions to be implemented in dynamically instantiated hardware units, combining adaptivity with hardware speed and efficiency. For the Intrusion Detection System example, new rules can be hardcoded into the reconfigurable logic, achieving high performance, while providing the necessary adaptivity to new threats. The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a complete methodology to allow designers to easily implement a system specification on a platform combining a general purpose processor with multiple accelerators running on an FPGA, taking as input a high-level description and fully exploiting, both at design- and run-time, the capabilities of partial dynamic reconfiguration. The FASTER project will facilitate the use of reconfigurable hardware by providing a complete methodology that enables designers to easily implement and verify applications on platforms with general-purpose processors and acceleration modules implemented in the latest reconfigurable technology

Smart technologies for effective reconfiguration: the FASTER approach

Current and future computing systems increasingly require that their functionality stays flexible after the system is operational, in order to cope with changing user requirements and improvements in system features, i.e. changing protocols and data-coding standards, evolving demands for support of different user applications, and newly emerging applications in communication, computing and consumer electronics. Therefore, extending the functionality and the lifetime of products requires the addition of new functionality to track and satisfy the customers needs and market and technology trends. Many contemporary products along with the software part incorporate hardware accelerators for reasons of performance and power efficiency. While adaptivity of software is straightforward, adaptation of the hardware to changing requirements constitutes a challenging problem requiring delicate solutions. The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a complete methodology to allow designers to easily implement a system specification on a platform which includes a general purpose processor combined with multiple accelerators running on an FPGA, taking as input a high-level description and fully exploiting, both at design time and at run time, the capabilities of partial dynamic reconfiguration. The goal is that for selected application domains, the FASTER toolchain will be able to reduce the design and verification time of complex reconfigurable systems providing additional novel verification features that are not available in existing tool flows

An FPGA-Based Real-Time System for 3D Stereo Matching, Combining Absolute Differences and Census with Aggregation and Belief Propagation

International audienceThe implementation of 3D stereo matching in real time is an important problem for many vision applications and algorithms. The current work, extending previous results by the same authors, presents in detail an architecture which combines the methods of Absolute Differences, Census, and Belief Propagation in an integrated architecture suitable for implementation with Field Programmable Gate Array (FPGA) logic. Emphasis on the present work is placed on the justification of dimensioning the system, as well as detailed design and testing information for a fully placed and routed design to process 87 frames per sec (fps) in $$1920 \times 1200$$ resolution, and a fully implemented design for $$400 \times 320$$ which runs up to 1570 fps

FASTER run-time reconfiguration management

The FASTER project Run-Time System Manager offloads programmers from low-level operations by performing task placement, scheduling, and dynamic FPGA reconfiguration. It also manages device fragmentation, configuration caching, pre-fetching and reuse, bitstream compression, and optimizes the system thermal and power footprints. We propose a micro-reconfiguration aware, configuration content agnostic ISA interface and a technology independent Task Configuration Microcode format targeting Maxeler Data Flow computers and Xilinx XUPV5 platforms. We achieve improved resource utilization with negligible performance overhead. Up to 4Gbps for DMA transfers, and up to 3Gbps for FPGA reconfiguration on Xilinx Virtex-5/6 devices is achieved

Experimental ATM Network Interface Performance Evaluation

Traditional methods of measuring network interface performance have been based on throughputsensitive benchmarks. However, the performance of an ever-increasing number of applications depends on the latency, and not on the throughput of the underlying communication network system. Experimental performance evaluation of latency and its constituent parts for high speed network interfaces of personal computers has not been studied in depth to date. We have developed performance evaluation methods that derive detailed PCI to ATM network interface latency results for personal computers, based on a combined software-hardware cooperation. Our methods address the seamless data collection of events that have six orders of magnitude difference in their duration, and range from user level requests down to segmentation latencies for packets within the network interface. As a result, all steps which contribute to the total transmission latency have been accurately measured for a specific network in..

Experimental ATM Network Interface Performance Evaluation

Traditional methods of measuring network interface performance have been based on throughputsensitive benchmarks. However, the performance of an ever-increasing number of applications depends on the latency, and not on the throughput of the underlying communication network system. Experimental performance evaluation of latency and its constituent parts for high speed network interfaces of personal computers has not been studied in depth to date. We have developed performance evaluation methods that derive detailed PCI to ATM network interface latency results for personal computers, based on a combined software-hardware cooperation. Our methods address the seamless data collection of events that have six orders of magnitude di erence in their duration, and range from user level requests down to segmentation latencies for packets within the network interface. As a result, all steps which contribute to the total transmission latency have been accurately measured foraspeci c network interface type. Experimental results derived with the new method arepresented, and its adaptation to vendor-independent measurements is described. Our experience suggests that measuring network interface latency using our methods is entirely feasible with equipment normally found in digital design laboratories. Furthermore it may lead toadeep understanding of the underlying communication system, which would be di cult (if not impossible) to acquire only with throughput-sensitive benchmarks