Fighting stochastic variability in a D-type flip-flop with transistor-level reconfiguration

In this study, the authors present a design optimisation case study of D-type flip-flop timing characteristics that are degraded as a result of intrinsic stochastic variability in a 25 nm technology process. What makes this work unique is that the design is mapped onto a multi-reconfigurable architecture, which is, like a field programmable gate array (FPGA), configurable at the gate level but can then be optimised using transistor level configuration options that are additionally built into the architecture. While a hardware VLSI prototype of this architecture is currently being fabricated, the results presented here are obtained from a virtual prototype implemented in SPICE using statistically enhanced 25 nm high performance metal gate MOSFET compact models from gold standard simulations for pre-fabrication verification. A D-type flip-flop is chosen as a benchmark in this study, and it is shown that timing characteristics that are degraded because of stochastic variability can be recovered and improved. This study highlights significant potential of the programmable analogue and digital array architecture to represent a next-generation FPGA architecture that can recover yield using post-fabrication transistor-level optimisation in addition to adjusting the operating point of mapped designs

Investigation into effects of device variability on CMOS layout motifs

Sub-circuit motifs are proposed as a methodology for simulating the performance of sub-45 nm circuits exhibiting atomistic device fluctuations. Motifs allow the reduction of the problem space and create a standard motif library as a step in the design hierarchy for logic circuits. Device variability information from 3D simulation results is used that is incorporated into families of BSIM4 models. It is demonstrated how a thorough understanding of circuit behaviour can be obtained and the impact on current drive is illustrated by examining the effect of additional parasitic resistance

Enhancement of Power and Frequency in HEMT-Like Planar Gunn Diodes by Introducing Extra Delta-Doping Layers

No abstract available

Enhancement of Power and Frequency in HEMT-Like Planar Gunn Diodes by Introducing Extra Delta-Doping Layers

No abstract available