Comparative study of power MOSFET device structures

980-988In this paper, a comprehensive comparative study of various power MOSFET device structures designed and developed during the past decade has been presented. Various design issues related with power MOSFET have been studied to look into their on-resistance (RON) versus breakdown voltage (Bv) trade off. Some of the existing power MOSFET device topologies have been compared with respect to their RON and Bv. The study reveals that the law-doped n epi region which gives square law relationship between <span style="mso-bidi-font-family: Arial;mso-bidi-language:HI">RON <span style="mso-bidi-font-family: Arial;mso-bidi-language:HI">and Bv in the conventional power MOSFET is being constantly engineered for optimizing <span style="mso-bidi-font-family: Arial;mso-bidi-language:HI">RON-Bv trade-off subsequently led to many structural modifications in its basic design giving rise to many new power MOSFET device structures such as SSCFET (Silicon Semiconductor Corp. FET), JBSFET (Junction barrier controlled Schottky FET), superjunction <span style="mso-bidi-font-family: Arial;mso-bidi-language:HI">(SJ)/COOLMOS™ <span style="mso-bidi-language: HI">transistor, semi-superjunction devices and FLlMOSFET (power MOSFETs with vertical floating islands) so as to overcome the conventional silicon limit. </span

Growth of nano-polycrystalline CuIn1-xAlxSe2 thin films and its photovoltaic cell formation

Nano-polycrystalline thin films of CuIn1-xAlxSe2 (CIAS) chalcopyrite material are re-grown on annealing the 700 nm thick Cu/In/Al/Se stack at temperatures ranging from 523 to 623 K. The stack is obtained at room temperature by sequentially evaporated layer deposition (SELD) technique. The grown films show a tetragonal crystal system of CIAS having unit cell parameters a; b = 5.781(5) Å, c = 11.593 (7) Å, with cell volume (V) = 387.523(4) Å3. The micrographs of the films show grains of spherical and cylindrical shapes. Raman spectra of the layers indicate A1 mode at 180.72(7) cm−1, which confirms the CIAS phase. The thin film's energy dispersive X-ray analysis (EDAX) establishes CuIn0.63Al0.37Se2 stoichiometry at 523 K. The direct allowed bandgap (Eg) value varies between 1.35 and 1.50 eV with a change in TA from 523 to 623 K; the values are near the optimum PV cell. The grown thin film samples exhibit absorption coefficient (α) ≥ 1 × 105 cm−1. The solar cell structure of FTO/p-CIAS/n-CdS/In exhibits a photovoltaic (PV) response

Novel power VDMOSFET structure with vertical floating islands and trench gate

301-307A novel power VDMOSFET (vertical double-diffused MOSFET) structure, simulated using PISCES-II, a 2-dimensional numerical device simulator has been described. The proposed device structure is based on the floating islands (FLI)-diode concept and trench gate technology. Extensive simulations were performed to understand physics of the device through various internal electrical quantities like potential distribution, electric field, etc. in different regions of the device both in on/off states.The simulation results show that the new device has a low on-resistance by virtue of reduced electric field in its drift region as well as due to the removal of parasitic JFET region resistance. Trench gate acts as a field plate to avoid the punch-through thus enhancing the breakdown voltage. For a 100 Volts design, an approximate 15% increase in the breakdown voltage has been observed in the proposed device compared to the conventional FLIMOSFET without trench gate

Investigation of a power FLIMOSFET based on two-dimensional numerical simulations

55-61This paper presents the numerical simulation results for a power FLIMOSFET structure with up to eleven vertical floating islands, designed using PISCES-IIB, a 2-dimensional advanced device simulator. The novel structure is based on the FLI-diode concept, which helps in lowering the maximum electrical field in the N–epitaxial region of the device to reduce the effective on–resistance without degrading device performance. Extensive simulations were performed to understand the device physics through various internal electrical quantities like potential distribution and electric field in different regions of the device both in on/off states. The effect of drift region doping on the device performance has been discussed. It is shown that the decrease in the drift region doping tends to decrease the electric field distribution and intermediate potential in this region thereby making its on-resistance lower than the value given by the conventional silicon limit. The device structure does not require any precise control of the boron implantation dose in the P+ floating islands for charge balance as essential in case of super junction (SJ)/COOLMOSTM devices. The process flow mechanism required to fabricate FLIMOSFET structure using multi-epitaxial technology has been discussed, which is less complex and less expansive than the super junction (SJ) devices technology

Processing of nanocrystalline thin films of selenium and formation of FTO/p-Se/n-CdS/In heterojunctions for photovoltaic response

Thin films of nanocrystalline selenium (Se) of different thicknesses were grown on annealing from 323 to 398 K. The crystallinity of the layers increased with annealing temperatures (TA). The temperature thickness correlations were established. The layers exhibited spherical-shaped particles at higher annealing temperatures. The grown layers possess hexagonal crystal system with space group P3121(152); it shows prominent planes along the a-axis. The bandgap (Eg) decreases from 2.18 to 1.94 eV, 2.12 to 1.82 eV, and 2.13 to 1.84 eV with changes in TA of 700, 270, and 150 nm thick layers, respectively. The high absorption coefficient (α) values ∼ 1 × 105 cm−1 observed in all films makes it suitable as an absorber layer in a solar cell structure and an optical sensor. The FTO/p-Se/n-CdS/In heterojunction diodes provide zero-bias barrier height (фbo) of 0.788(7) eV. The open circuit voltage (Voc) of FTO/p-Se (150 nm)/n-CdS(200 nm)/In a photovoltaic cell was observed to be 55 mV

Impact of annealing on the growth dynamics of indium sulphide buffer layers

Thin films of Indium sulphide are deposited on corning glass substrate by thermal evaporation at room temperature (300 K). The as-deposited films were annealed from 373 to 723 K under vacuum ∼1 × 10−3 mbar. An amorphous phase is obtained from 300 to 473 K; the polycrystalline β-In2S3 emerges at 523 K, and In2O3 is grown at 723 K. The intermediary phases of β-In2S3 and In2O3 are perceived from 573 to 673 K. A clear distinction between the morphology of β-In2S3 and In2O3 was observed in the micrographs of scanning electron microscopy (SEM) and atomic force microscopy (AFM). The β-In2S3 dominated films provide absorption coefficient (α) from 18 to 25 × 104 cm−1, while α values of In2O3 layers lie within 1–5 × 104 cm−1. The bandgap (Eg) of β-In2S3 thin films is low (2.34 eV), and that of In2O3 is high (3.47 eV); however, the intermediary phases of β-In2S3 and In2O3 exhibit bandgap tunning from 2.30 to 3.14 eV. Moreover, the β-In2S3 shows the highest carrier concentration (Nd; 3.25 × 1018 cm−3), In2O3 provides the highest mobility (μ; 228 Cm2/V.s), and intermediary phases exhibit the lowest resistivity (ρ; 1.27 × 103 Ω/cm) within the existing forms. The thin films β-In2S3 phase grown at 523 and 573 K meet its stoichiometric ratio. In comparison, the In2O3 phase emerges under high oxygen and sulphur deficit conditions. The films are suitable for photo-conduction devices and in the buffer/window layer of PV solar cell design

A Two-step Method to Grow ZnSe Thin Films and to Study their Characteristics

739-743The ZnSe material synthesised by the fusion method was used to deposit 200 nm thin layers on corning glass substrate at 300 K in a vacuum (2x10-6 mbar). The as-deposited films were annealed at 573 K in a vacuum (1x10-3 mbar). The obtained crystallites provide the most significant peak (MSP) along (111) orientations corresponding to a zinc blende structure. Further, the grown samples show maximum transmittance of ~ 90% in visible - NIR regions of the E M Spectrum. The layers possess the direct bandgap (Eg) of 2.02 (300 K) and 2.57 eV (573 K). The surface morphology indicates the uniform spread of nanocrystalline particles over the substrate. Thus, the obtained ZnSe films are useful as buffer/window layers in solar cell structures

<span style="font-size: 22.0pt;mso-bidi-font-size:15.0pt;font-family:"Times New Roman","serif"; mso-bidi-font-weight:bold">Study of dark and photoconductivity of Sb-doped CuInSe_{<span style="font-size:16.5pt;mso-bidi-font-size:9.5pt;font-family:"Arial","sans-serif"; mso-bidi-font-weight:bold">2</span>}<span style="font-size:16.5pt; mso-bidi-font-size:9.5pt;font-family:"Arial","sans-serif";mso-bidi-font-weight: bold"> <span style="font-size:22.0pt;mso-bidi-font-size:15.0pt; font-family:"Times New Roman","serif";mso-bidi-font-weight:bold">thin films </span></span></span>

723-726<span style="font-size: 15.5pt;mso-bidi-font-size:8.5pt;font-family:" times="" new="" roman","serif""="">Dark and photoconductivity measurements of un-doped and Sb-doped CuInSe2 (CIS) films prepared by pulsed laser deposition technique, using ArF laser have been reported. The dark and photoconductivity of Sb-doped films have been found to be higher, compared to <span style="font-size:13.0pt;mso-bidi-font-size: 6.0pt;font-family:HiddenHorzOCR;mso-hansi-font-family:" times="" new="" roman";="" mso-bidi-font-family:hiddenhorzocr"="">the <span style="font-size:15.5pt; mso-bidi-font-size:8.5pt;font-family:" times="" new="" roman","serif""="">un-doped CIS films. Recombination mechanism has also been discussed in the doped <span style="font-size: 15.5pt;mso-bidi-font-size:8.5pt;font-family:" times="" new="" roman","serif""="">and un-doped films. </span

Modeling power VDMOSFET transistors: Device physics and equivalent circuit model with parameter extraction

775-782 A power VDMOSFET has been simulated using PISCES-II, a 2-D numerical device simulator. The doping densities and device dimensions are chosen so as to simulate a typical device structure with one micron channel length. These simulations are aimed at understanding the device physics through various internal electrical quantities like potential distribution, electric field distribution, and electron concentrations etc. in different regions of the device both in on/off states. Simulated results have been used to extract circuit model parameters like VT, KP and λ etc. for a VDMOSFET equivalent circuit model comprising of a lateral MOSFET in series with a JFET. It advances the earlier models in terms of number of parameters extracted for its SPICE implementation. The characteristics obtained from the dc circuit model show good agreement with the simulated data, thus validating the device operation, the circuit model and its parameter extraction procedures