High temperature reliability of power module substrates

The thermal cycling reliability of candidate copper and aluminium power substrates has been assessed for use at temperatures exceeding 300°C peak using a combination of thermal cycling, nanoindentation and finite element modelling to understand the relative stresses and evolution of the mechanical properties. The results include the relative cycling lifetimes up to 350°C, demonstrating almost an order of magnitude higher lifetime for active metal brazed Al / AlN substrates over Cu / Si3N4, but four times more severe roughening and cracking of the Ni-P plating's on the Al / AlN (DBA) substrates. The nonlinear finite element modelling illustrated that the yield strength of the metal and the thickness of the ceramic are the main stress controlling factors, but comparisons with the cycling lifetime results demonstrated that the fracture toughness (resistance) of the ceramic is the over-riding controlling factor for the overall passive thermal cycling lifetimes. In order to achieve the highest substrate lifetime for the highly stressed high temperature thermal cycled applications, the optimum solution appears to be annealed copper, brazed on to a thicker than normal or higher fracture toughness Si3N4 ceramic

Analysis of linear-doped Si/SiC power LDMOSFETs based on device simulation

This paper presents the design and optimization of a 600 V silicon-on-silicon carbide (Si/SiC) laterally diffused MOSFET with linear doping profile in the drift region for high-temperature applications. The proposed structure has an embedded silicon-on-insulator (SOI) layout through which the traditional graded doping theory for SOI can be applied in the Si/SiC architecture. An SOI counterpart is introduced as a benchmark and modeled alongside the proposed structure. Comparisons between them show that they have the near-identical OFF-state and breakdown characteristics, with a significant tunneling leakage component emerging above 450 V. In the ON state, the Si/SiC device has higher electrical resistance but much lower thermal resistance, leading to less self-heating and higher reliability

Simulation of a new hybrid Si/SiC power device for harsh environment applications

A new power device structure is proposed, conceived to operate in a high temperature, harsh environment, for example within a motor drive application down hole, as an inverter in the engine bay of an electric car, or as a solar inverter in space. The lateral silicon power device resembles a laterally diffused MOSFET (LDMOS), such as those implemented within silicon on insulator (SOI) substrates. However, unlike SOI, the Si thin film has been transferred directly onto a semi-insulating 6H silicon carbide (6H-SiC) substrate via a wafer bonding process. Thermal simulations of the hybrid Si/SiC substrate have shown that the high thermal conductivity of the SiC will have a junction-to-case temperature approximately 4 times less that an equivalent SOI device, reducing the effects of self-heating. Electrical simulations of a 600 V power device, implemented entirely with the silicon thin film, suggest that it will retain the ability of SOI to minimise leakage at high temperature, but does so with 50% less conduction losses

Accurate analytical modeling for switching energy of PiN diodes reverse recovery

PiN diodes are known to significantly contribute to switching energy as a result of reverse-recovery charge during turn-off. At high switching rates, the overlap between the high peak reserve-recovery current and the high peak voltage overshoot contributes to significant switching energy. The peak reverse-recovery current depends on the temperature and switching rate, whereas the peak diode voltage overshoot depends additionally on the stray inductance. Furthermore, the slope of the diode turn-off current is constant at high insulated-gate bipolar transistor (IGBT) switching rates and varies for low IGBT switching rates. In this paper, an analytical model for calculating PiN diode switching energy at different switching rates and temperatures is presented and validated by ultrafast and standard recovery diodes with different current ratings. Measurements of current commutation in IGBT/PiN diode pairs have been made at different switching rates and temperatures and used to validate the model. It is shown here that there is an optimal switching rate to minimize switching energy. The model is able to correctly predict the switching rate and temperature dependence of the PiN diode switching energies for different devices

Analytical modeling of switching energy of silicon carbide Schottky diodes as functions of dIDS/dt and temperature

SiC Schottky Barrier diodes (SiC SBD) are known to oscillate/ring in the output terminal when used as free-wheeling diodes in voltage-source converters. This ringing is due to RLC resonance among the diode capacitance, parasitic resistance, and circuit stray inductance. In this paper, a model has been developed for calculating the switching energy of SiC diodes as a function of the switching rate (dIDS/dt of the commutating SiC MOSFET) and temperature. It is shown that the damping of the oscillations increases with decreasing temperature and decreasing dIDS/dt. This in turn determines the switching energy of the diode, which initially decreases with decreasing dIDS/dt and subsequently increases with decreasing dIDS/dt thereby indicating an optimal dIDS/dt for minimum switching energy. The total switching energy of the diode can be subdivided into three phases namely the current switching phase, the voltage switching phase, and the ringing phase. Although the switching energy in the current switching phase decreases with increasing switching rate, the switching energy of the voltage and ringing phase increases with the switching rate. The model developed characterizes the dependence of diode's switching energy on temperature and dIDS/dt, hence, can be used to predict the behavior of the SiC SBD

A study of temperature-related non-linearity at the metal-silicon interface

In this paper, we investigate the temperature dependencies of metal-semiconductor interfaces in an effort to better reproduce the current-voltage-temperature (IVT) characteristics of any Schottky diode, regardless of homogeneity. Four silicon Schottky diodes were fabricated for this work, each displaying different degrees of inhomogeneity; a relatively homogeneous NiV/Si diode, a Ti/Si and Cr/Si diode with double bumps at only the lowest temperatures, and a Nb/Si diode displaying extensive non-linearity. The 77–300 K IVT responses are modelled using a semi-automated implementation of Tung's electron transport model, and each of the diodes are well reproduced. However, in achieving this, it is revealed that each of the three key fitting parameters within the model display a significant temperature dependency. In analysing these dependencies, we reveal how a rise in thermal energy “activates” exponentially more interfacial patches, the activation rate being dependent on the carrier concentration at the patch saddle point (the patch's maximum barrier height), which in turn is linked to the relative homogeneity of each diode. Finally, in a review of Tung's model, problems in the divergence of the current paths at low temperature are explained to be inherent due to the simplification of an interface that will contain competing defects and inhomogeneities

Comparative study of RESURF Si/SiC LDMOSFETs for high-temperature applications using TCAD modeling

This paper analyses the effect of employing an Si on semi-insulating SiC (Si/SiC) device architecture for the implementation of 600-V LDMOSFETs using junction isolation and dielectric isolation reduced surface electric field technologies for high-temperature operations up to 300 °C. Simulations are carried out for two Si/SiC transistors designed with either PN or silicon-on-insulator (SOI) and their equivalent structures employing bulk-Si or SOI substrates. Through comparisons, it is shown that the Si/SiC devices have the potential to operate with an offstate leakage current as low as the SOI device. However, the low-side resistance of the SOI LDMOSFET is smaller in value and less sensitive to temperature, outperforming both Si/SiC devices. Conversely, under high-side configurations, the Si/SiC transistors have resistances lower than that of the SOI at high substrate bias, and invariable with substrate potential up to −200 V, which behaves similar to the bulkSi LDMOS at 300 K. Furthermore, the thermal advantage of the Si/SiC over other structures is demonstrated by using a rectangle power pulse setup in Technology Computer-Aided design simulations

An evaluation of silicon carbide unipolar technologies for electric vehicle drive-trains

Voltage sourced converters (VSCs) in electric vehicle (EV) drive-trains are conventionally implemented by silicon Insulated Gate Bipolar Transistors (IGBTs) and p-i-n diodes. The emergence of SiC unipolar technologies opens up new avenues for power integration and energy conversion efficiency. This paper presents a comparative analysis between 1.2-kV SiC MOSFET/Schottky diodes and silicon IGBT/p-i-n diode technologies for EV drive-train performance. The switching performances of devices have been tested between -75 °C and 175 °C at different switching speeds modulated by a range of gate resistances. The temperature impact on the electromagnetic oscillations in SiC technologies and reverse recovery in silicon bipolar technologies is analyzed, showing improvements with increasing temperature in SiC unipolar devices whereas those of the silicon-bipolar technologies deteriorate. The measurements are used in an EV drive-train model as a three-level neutral point clamped VSC connected to an electric machine where the temperature performance, conversion efficiency and the total harmonic distortion is studied. At a given switching frequency, the SiC unipolar technologies outperform silicon bipolar technologies showing an average of 80% reduction in switching losses, 70% reduction in operating temperature and enhanced conversion efficiency. These performance enhancements can enable lighter cooling and more compact vehicle systems

The impact of temperature and switching rate on the dynamic characteristics of silicon carbide schottky barrier diodes and MOSFETs

Silicon carbide Schottky barrier diodes (SiC-SBDs) are prone to electromagnetic oscillations in the output characteristics. The oscillation frequency, peak voltage overshoot, and damping are shown to depend on the ambient temperature and the metal-oxide- semiconductor field-effect transistor (MOSFET) switching rate (dIDS/dt). In this paper, it is shown experimentally and theoretically that dIDS/dt increases with temperature for a given gate resistance during MOSFET turn-on and reduces with increasing temperature during turn-off. As a result, the oscillation frequency and peak voltage overshoot of the SiC-SBD increases with temperature during diode turn-off. This temperature dependence of the diode ringing reduces at higher dIDS/dt and increases at lower dIDS/dt. It is also shown that the rate of change of dIDS/dt with temperature (d2IDS/dtdT) is strongly dependent on RG and using fundamental device physics equations, this behavior is predictable. The dependence of the switching energy on dIDS/dt and temperature in 1.2-kV SiC-SBDs is measured over a wide temperature range (-75 °C to 200 °C). The diode switching energy analysis shows that the losses at low dIDS/dt are dominated by the transient duration and losses at high dIDS/dt are dominated by electromagnetic oscillations. The model developed and results obtained are important for predicting electromagnetic interference, reliability, and losses in SiC MOSFET/SBDs

Paranoid thinking, cognitive bias and dangerous neighbourhoods: implications for perception of threat and expectation of victimisation

Background: Paranoid thinking is prevalent in the non-clinical population and cognitive mechanisms of heuristic reasoning and jumping to conclusions bias contributes to its formation and maintenance. Aims: This study investigated the degree to which paranoia, perceived environmental risk, heuristic reasoning and jumping to conclusions bias (measured with the beads task) contribute to misinterpretation of neutral stimuli, and whether this informed judgements regarding vulnerability to threat and crime. It is also investigated whether impulsiveness is a confounding factor on the beads task. Methods: Two hundred participants were recruited using a snowball-sampling method for a quantitative cross-sectional study. Participants reported demographic information, three psychometric questionnaires and two experimental tasks via an online paradigm hosted by the Bristol Online Survey tool. Results: Participants with high paranoia scores perceived their environment to be more dangerous than those with low scores. Participants with high paranoia scores also overestimated threat in neutral stimuli and had high expectations of future victimisation. Jumping to conclusions on the beads task did not predict fear of crime outcomes, but was predicted by impulsivity. Conclusion: Participants who demonstrated paranoid thinking were more likely to reside in perceived dangerous neighbourhoods and overestimate threat. While this could indicate a paranoid heuristic, it is a potentially rational response to prior experiences of crime and victimisation. Implications and suggestions for future research are discussed