A new time-dependent mobility degradation model for MOS transistors

Purpose - The purpose of this paper is to propose a time-dependent mobility degradation model which is independent from the process or operating conditions

Characterization and modeling of power MOSFET switching times variations under constant electrical stress

In this paper, we proposed a simple and accurate degraded power MOSFET model for digital applications. The model provides to determine the electrical stress induced changes in power MOSFET switching characteristics. To establish the degraded power MOSFET and stress induced changes in switching parameters relation we consider the on-state-resistance of the power MOSFET as a voltage controlled resistor. We implemented a voltage non-linearly dependent resistor model in Pspice. We compared the experimental and simulation results to explore the model capability. (C) 2015 Elsevier Ltd. All rights reserved

Modelling of degraded power MOSFET effects on inverter static parameters

In this study, electrical constant stress method which is one of accelerated tests is applied to power vertical double diffused MOSFETs continued up to 6 hours. The stress induced changes of characteristic parameters (threshold voltage, mobility, etc.) of power MOSFETs are extracted. A resistive load NMOS inverter is set up and degraded power MOSFET effects on its static parameters are investigated experimentally. Besides the obtained experimental results, a simple circuit model is proposed to simulate the stress induced changes in NMOS inverter static parameters. In this manner, obtained experimental results are supported by simulation study. Proposed degradation model has ability to help designers to predict circuit reliability in the early stages of design. (C) 2015 Elsevier Ltd. All rights reserved. Selection and Peer-review under responsibility of Conference Committee Members of International Semiconductor Science and Technology Conference 2015 (ISSTC 2015)

Investigation of VDMOSFET's switching power dissipation changes under constant electrical stress

This study aims to examine the electrical stress effects on the switching power dissipation in n-channel VDMOSFET. We set up a resistive load NMOS inverter as a WA circuit. At first step of measurement, VDMOSFETs are subjected to the high constant voltage (55V(DC)) up to 6 h and this degradation process is continued until just prior to the oxide breakdown. Stress induced changes in output voltage and current are extracted using the resistive load NMOS inverter. The static and dynamic power dissipations, and power-delay product are calculated accordingly. In addition, assuming that the inverter load is selected as n-channel VDMOSFET, the power dissipation is calculated. In resistive load NMOS inverter, it is observed that the static power dissipation is decreased by 5.3%, the dynamic power is increased by around 60% and the total power dissipation is decreased by 5% compared to before the stress. In enhancement load NMOS inverter, the total power dissipation has a decrease of around 92%

A New Approach for VDMOSFETs' Gate Oxide Degradation Based on Capacitance and Subthreshold Current Measurements Under Constant Electrical Stress

In this brief, we proposed a new gate oxide degradation model for vertical double diffused MOS devices under constant electrical stress. To form a complete model, we separated the changes associated with gate oxide and Si-SiO2 interface. We presented oxide trap-induced gate oxide and interface trap-induced Si-SiO2 interface degradation effects on the model, separately. We used capacitance measurements for gate oxide and subthreshold current measurements for Si-SiO2 interface degradation. We presented the survive of the stress-induced gate oxide and interface capacitances during stress time. We also expressed the mathematical expressions for parts of the proposed model

On the reliability of symmetrical CMOS OTA operating in subthreshold region

CMOS circuits such as OTAs (operational transconductance amplifiers) operating in the subthreshold (weak inversion) region introduce a versatile solution for the realization of low-power VLSI building blocks. In this paper, hot carrier induced degradation of electrical parameters of CMOS OTAs operating in subthreshold region is investigated by accelerated laboratory measurements. Using the experimental observations a degradation model is proposed for reliability of CMOS OTA. The advantages provided by the degradation model proposed is demonstrated by experiments on design examples of first and second order OTA-C filters. The estimated results are found in good agreement with experiments. The model proposed provides to the IC designer new possibilities to estimate the reliability of OTA-C based topologies operating in subthreshold region