Offdiagonal Complexity: A computationally quick complexity measure for graphs and networks

A vast variety of biological, social, and economical networks shows topologies drastically differing from random graphs; yet the quantitative characterization remains unsatisfactory from a conceptual point of view. Motivated from the discussion of small scale-free networks, a biased link distribution entropy is defined, which takes an extremum for a power law distribution. This approach is extended to the node-node link cross-distribution, whose nondiagonal elements characterize the graph structure beyond link distribution, cluster coefficient and average path length. From here a simple (and computationally cheap) complexity measure can be defined. This Offdiagonal Complexity (OdC) is proposed as a novel measure to characterize the complexity of an undirected graph, or network. While both for regular lattices and fully connected networks OdC is zero, it takes a moderately low value for a random graph and shows high values for apparently complex structures as scale-free networks and hierarchical trees. The Offdiagonal Complexity apporach is applied to the Helicobacter pylori protein interaction network and randomly rewired surrogates.Comment: 12 pages, revised version, to appear in Physica

PLL-based high-speed demodulation of FM signals for real-time AFM applications

In this paper we present a new architecture for PLL-based high-speed demodulation of frequency-modulated AFM signals. In our approach, we use single-sideband frequency up-conversion to translate the AFM signal from the position sensitive detector to a fixed intermediate frequency of 10MHz. In this way, we fully benefit from the excellent noise performance of PLL-based FM demodulators still avoiding the intrinsic bandwidth limitation of such systems. Furthermore, the system becomes independent of the cantilever's resonance frequency. To investigate if the additional noise introduced by the single-sideband upconverter degrades the system noise figure we present a model of the AM-to-FM noise conversion in the PLL phase detector. Using this model, we can predict an upper corner frequency for the demodulation bandwidth above which the converted noise from the single-sideband upconverter becomes the dominant noise source and therefore begins to deteriorate the overall system performance. The approach is validated by measured data obtained with a PCB-based prototype implementing the proposed demodulator architecture. © 2013 IEEE

Single-Cycle-PLL Detection for Real-Time FM-AFM Applications

In this paper we present a novel architecture for phase-locked loop (PLL) based high-speed demodulation of fre- quency-modulated (FM) atomic force microscopy (AFM) signals. In our approach, we use single-sideband (SSB) frequency upcon- version to translate the AFM signal from the position sensitive detector to a fixed intermediate frequency (IF) of 10 MHz. In this way, we fully benefit from the excellent noise performance of PLL-based FM demodulators still avoiding the intrinsic band- width limitation of such systems. In addition, the upconversion to a fixed IF renders the PLL demodulator independent of the cantilever’s resonance frequency, allowing the system to work with a large range of cantilever frequencies. To investigate if the additional noise introduced by the SSB upconverter degrades the system noise figure we present a model of the AM-to-FM noise conversion in PLLs incorporating a phase-frequency detector. Using this model, we can predict an upper corner frequency for the demodulation bandwidth above which the converted noise from the single-sideband upconverter becomes the dominant noise source and therefore begins to deteriorate the overall system performance. The approach is validated by both electrical and AFM measurements obtained with a PCB-based prototype imple- menting the proposed demodulator architecture

A new optimization approach for the automatic design of Sigma Delta-modulators

In this paper, a new methodology for the automated design of one-bit internal quantizer Sigma Delta-modulators is presented. The core of the method is an NTF prototype generation in the DT-domain based on the quasilinear quantizer modeling, that maximizes the maximum stable amplitude (MSA) of the modulator while achieving a certain minimum peak SNDR. For CT-modulators, this is followed by a DT-CT mapping of the loop filter in state-space. The improved MSA allows for higher circuit noise and thus greatly relaxes the area and power consumption constraints of the design. Simulation results at the end of the paper verify the validity of the method

A low-power high-sensitivity single-chip receiver for NMR microscopy

In this paper, we present a fully-integrated receiver for NMR microscopy applications manufactured in a 0.13 mu m CMOS technology. The design co-integrates a 10-turn planar detection coil together with a complete quadrature, low-IF downconversion receiver on a single chip, which operates from a single 1.5 V supply with a total power dissipation of 18 mW. The detector's measured time-domain spin sensitivity is 3 x 10(13) H-1 spins/root Hz at 7 T. Additionally, the paper discusses two important aspects of NMR microscopy using planar detection coils: the link between the detection coil's spin sensitivity and the achievable image SNR and the correction of image artifacts induced by the inhomogeneous sensitivity profile of planar detection coils. More specifically, we derive analytical expressions for both the theoretical image SNR as a function of the coil's spin sensitivity and the sensitivity correction for a known coil sensitivity profile in CTI MR imaging experiments. Both expressions are validated using measured data in the imaging section of the paper. Thanks to the improved spin sensitivity of the utilized integrated receiver chip compared to a previously presented design, we were able to obtain sensitivity corrected images in a 7 T spectroscopy magnet with isotropic resolutions of 9.6 mu m and 5 mu m with single-shot SNRs of 37 and 15 in relatively short imaging times of 4.4 h and 24 h, respectively. (C) 2016 Elsevier Inc. All rights reserved

An Integrator-Differentiator TIA Using a Multi-Element Pseudo-Resistor in its DC Servo Loop for Enhanced Noise Performance

In this paper, we present an integrator-differentiator transimpedance amplifier (TIA) featuring a multielement pseudo-resistor (MEPR) in the DC feedback path for improved noise performance in the presence of non-zero DC input currents. The presented prototype is implemented in a standard 180 nm CMOS technology and achieves an inband transimpedance of 10 M Omega over a 2.7 MHz signal bandwidth. The MEPR resistor in the DC servo loop can be tuned between 700 k Omega and 100 M Omega enabling a precise adjustment of the TIA's lower cutoff frequency. For a DC feedback resistance of 700 k Omega, the TIA provides an input referred noise floor of 180 fA/root Hz at zero input current, which only marginally increases to 220 fA/root Hz for the maximum bias current of 1 mu A. The TIA consumes 0.6 mm(2) of chip area and 18.5 mW of power from a 1.8 V supply