Event-driven spiking convolutional neural network

The invention relates to an event-driven spiking convolutional neural network, comprising a plurality of layers, wherein each layer comprises - a kernel module configured to store and to process in an event-driven fashion kernel values of at least one convolution kernel, - a neuron module configured to store and to process in an event-driven fashion neuron states of neurons of the network, and particularly to output spike events generated from the updated neurons, - a memory mapper configured to determine neurons to which an incoming a spike event from a source layer projects to by means of a convolution with the at least one convolution kernel and wherein neuron states of said determined neurons are to be updated with applicable kernel values of the at least one convolution kernel, wherein the memory mapper is configured to process incoming spike events in an event-driven fashion.</p

Event-driven integrated circuit having interface system

The present invention relates to an event-driven integrated circuit, comprising a sensor, an interface system and a processor. By means of the solution, events with addresses are asynchronously generated and processed. The interface system comprises a replication module, a fusion module, a secondary sampling module, a region of interest module, an event routing module, etc., which constitute a programmable daisy chain. The sensor, the interface system and the processor are coupled on a single chip by means of an adapter board, and different bare dies can be manufactured by using different processes. By means of the solution, signal loss and noise interference in the prior art can be eliminated, and the technical effects of high-speed processing of signals, smaller footprints of chips, reduced manufacturing costs, etc., are achieved, thereby solving the technical problems in the prior art of a large chip area and a low signal processing capability. In addition, by means of the smart design of the interface system, the functions and configurability of the interface system are enriched, thereby providing various advantages in terms of power consumption, functions and speed in subsequent processing