The ABC130 barrel module prototyping programme for the ATLAS strip tracker

For the Phase-II Upgrade of the ATLAS Detector, its Inner Detector, consisting of silicon pixel, silicon strip and transition radiation sub-detectors, will be replaced with an all new 100 % silicon tracker, composed of a pixel tracker at inner radii and a strip tracker at outer radii. The future ATLAS strip tracker will include 11,000 silicon sensor modules in the central region (barrel) and 7,000 modules in the forward region (end-caps), which are foreseen to be constructed over a period of 3.5 years. The construction of each module consists of a series of assembly and quality control steps, which were engineered to be identical for all production sites. In order to develop the tooling and procedures for assembly and testing of these modules, two series of major prototyping programs were conducted: an early program using readout chips designed using a 250 nm fabrication process (ABCN-25) and a subsequent program using a follow-up chip set made using 130 nm processing (ABC130 and HCC130 chips). This second generation of readout chips was used for an extensive prototyping program that produced around 100 barrel-type modules and contributed significantly to the development of the final module layout. This paper gives an overview of the components used in ABC130 barrel modules, their assembly procedure and findings resulting from their tests.Comment: 82 pages, 66 figure

Ambidextrous Catalytic Access to Di­thieno­[3,2‑<i>b</i>:2′,3′‑<i>d</i>]­thio­phene (DTT) Derivatives by Both Palladium-Catalyzed C–S and Oxidative Dehydro C–H Coupling

A modular two-step synthesis of dithieno­[3,2-<i>b</i>:2′,3′-<i>d</i>]­thio­phene (DTT) derivatives by C–S cross-coupling and oxidative dehydro C–H coupling is herein described. Dibenzo­[<i>d,d</i>′]­thieno­[3,2-<i>b</i>;4,5-<i>b</i>′]­dithio­phene (DBTDT) and associated two donor (anisyl) and acceptor (acetyl) substituted DTT derivatives were synthesized by palladium-catalyzed cross-coupling sequences in 17% to 71% yield over two steps. The 5,5′-disubstituted DTT derivatives were characterized in terms of their photophysical (UV and fluorescence spectroscopy) and electrophysical (cyclovoltammography) properties

Functionality and performance of the ALFA_CTPIN module

The ALFA_CTPIN module has been designed in response to increased internal processing time of the Central Trigger Processor (CTP) of the ATLAS experiment which resulted in reducing time left to the ALFA detector to deliver its own triggers to the CTP within specified latency. Accelerated extraction of ALFA triggers from encoded signals and the possibility to perform local triggers processing by this module allowed ALFA to contribute to global triggering of the ATLAS detector. A huge number of implemented scalers and flexibility in defining triggers processing criteria make also from this module a very attractive tool for in-depth analysis of properties of the LHC beam

The End-of-Substructure Card for the ATLAS ITk Strip Detector: Status of the Electronics Design and Results from Recent Quality Control Tests

The silicon tracker of the ATLAS experiment will be upgraded for the upcoming High-Luminosity Upgrade of the LHC (HL-LHC). The main building blocks of the new strip tracker are modules that consist of silicon sensors and read-out ASICs, the latter hosted on hybrid PCBs. Up to 14 modules are assembled on carbon-fibre substructures, commonly named staves in the central barrel region and petals in the two end-cap regions, for mechanical support. An End-of-Substructure (EoS) card is located at the end of each substructure and facilitates the transfer of data, power, and control signals between the modules and the off-detector systems. The module front-end ASICs transfer data (up to 28 differential lines at 640 MBit/s) to low-powered GigaBit Transceivers (lpGBT) ASICs on the EoS card. The lpGBT(s) provide data serialisation and use a 10 GBit/s versatile optical link plus transceiver (VTRx+) package to transmit signals to the off-detector systems. To meet the tight integration requirements in the detector, several EoS card designs have been realised. The produced prototypes have been populated with the currently available versions of the lpGBT and VTRx+ ASICs. Here, we present the current status of the EoS cards electronic design, results from extreme temperature, magnetic field and integration tests. Additionally, we discuss the results of detailed investigations into the optical signal quality and introduce a new eye-diagram extraction tool to be used in the Quality Control (QC) procedure that aims to ensure full functionality of the EoS card throughout the entire HL-LHC operation

Current status of the end-of-substructure (EoS) card project for the ATLAS strip tracker upgrade using final ASICs

In the context of the high-luminosity upgrade of the LHC and ATLAS, the microstrip-tracking detector will be redesigned. The main building blocks are substructures with multiple sensors and their electronics. Each substructure will have a single interface to the off-detector system, the so-called End-of-Substructure (EoS) card. Its physical realisation is a set of printed circuit boards (PCBs). The PCB integrates ASICs and hybrids, which multiplex or demultipex the data and transmit with a rate up to 10 Gb/s or receive with a rate up to 2.5 Gb/s on optical fibres. These active parts are developed at CERN and are known as lpGBT and VTRx+. The EoS card integrates the active parts with the required electronics for the specified operation and within the mechanical constraints of the detector. In this paper critical design aspects such as the low-impedance powering scheme and the PCB setup are described. The EoS card has reached its final state for a series production, including the required setups for quality control. The achieved transmission quality on the 10 Gb/s links is presented

Current status of the End-of-Substructure (EoS) card project for the ATLAS Strip Tracker Upgrade using final ASICs

The silicon tracker of the ATLAS experiment will be upgraded for the upcoming High-Luminosity Upgrade of the LHC (HL-LHC). The main building blocks of the new strip tracker are modules that consist of silicon sensors and hybrid PCBs hosting the read-out ASICs. The modules are mounted on rigid carbon-fibre substructures, that provide common services to all the modules. At the end of each substructure, a so-called End-of-Substructure (EoS) card facilitates the transfer of data, power, high voltage and control signals between the modules and the off-detector systems. The module front-end electronics transfer data to the EoS card on 640Mbit/s differential lines. The EoS connects up to 28 data lines to one or two lpGBT chips that provide data serialisation and uses a 10GBit/s versatile optical link (VTRx+) to transmit signals to the off-detector systems. The lpGBT also recovers the LHC clock on the down-link and generates clock and control signals for the modules. To meet the tight integration requirements in the detector, several different EoS card designs are needed. Production-ready EoS card’s electronic design integrating final lpGBTv1 and VTRx+ ASICs from CERN are described, as well as results from recent quality assurance tests including detailed characterisation of the opto-electronics system by its bit error rate, jitter, and eye diagram representation. Since each EoS sits at a single-point-of-failure for an entire side of a substructure, a dedicated quality control (QC) procedure for the production has been developed