An Integrated Radar Tile for Digital Beamforming X-/Ka-Band Synthetic Aperture Radar Instruments

This paper presents the first experimental assessment of a highly integrated dual-band dual-polarized antenna tile designed for synthetic aperture radar (SAR) digital beamforming (DBF) satellite applications. The demonstrator described in this paper is the first comprehensive experimental validation of an RF module providing the X-band and Ka-band (9.6- and 35.75-GHz) operation with custom downconversion stages. All the antennas, transitions, and downconversion chips are integrated in the same antenna tile fabricated using a customized 15-layer high density interconnect process. The designed tile goes to the limits of the proposed technology and for the high trace density and for the size of the vertical transitions. The proposed results represent the state of the art in terms of compactness for a DBF SAR RF module even though the demonstrator was manufactured with a standard low-cost technology. The experimental assessment proves the validity of the proposed manufacturing and integration approaches showing a substantial agreement between the performance of the individual blocks and of the integrated system

Exploring the Performance-Energy Optimization Space of a Bridge Between 3D-Stacked Electronic and Optical Networks-on-Chip

The relentless improvement of silicon photonics is making optical interconnects and networks appealing for use in miniaturized systems, where electrical interconnects cannot keep up with the growing levels of core integration due to bandwidth density and power efficiency limitations. At the same time, solutions such as 3D stacking or 2.5D integration open the door to a fully dedicated process optimization for the photonic die. However, an architecture-level integration challenge arises between the electronic network and the optical one in such tightly-integrated parallel systems. It consists of adapting signaling rates, matching the different levels of communication parallelism, handling cross-domain flow control, addressing re-synchronization concerns, and avoiding protocol-dependent deadlock. The associated energy and performance overhead may offset the inherent benefits of the emerging technology itself. This paper explores a hybrid CMOS-ECL bridge architecture between 3D-stacked technology-heterogeneous networks-on-chip (NoCs). The different ways of overcoming the serialization challenge (i.e., through an improvement of the signaling rate and/or through space-/wavelength-division multiplexing options) give rise to a configuration space that the paper explores, in search for the most energy-efficient configuration for high-performance

R-Abax: A radiation hardening legalisation algorithm satisfying TMR spacing constraints

Faults caused by ionising radiation have become a significant reliability issue in modern ICs. However, the Radiation Hardening (RADHARD) design flow differs from the standard design flow. Thus, there is not sufficient support from industrial EDA tools. In this work, we present a Triple Modular Redundancy (TMR) Radiation Hardening (RADHARD) methodology, based on the replacement of Flip-Flops (FFs) to a TMR structure, consisting of a FF triplet and a majority voter, as well as a custom, Displacement-driven legalisation algorithm, called R-Abax, able to satisfy user-specified, minimum distances between the FFs of each triplet. Our RADHARD legalisation algorithm is fully compatible with existing EDA tools. By ensuring a minimum spacing between triplet FFs of each TMR structure, we reduce the probability of a particle strike affecting more than one triplet instances. We present the impact of our RADHARD flow, for a set of spacing constraints, to Power, Performance and Area (PPA) on a set of 11 OpenCores benchmarks. On average, a larger spacing between FF triplets worsens a design's Quality-of-Results (QoR), but not significantly, making our RADHARD flow attractive for reducing radiation faults. © 2020 IEEE

Interfacing 3D-stacked electronic and optical NoCs with mixed CMOS-ECL bridges: A realistic preliminary assessment

The combination of optical networks-on-chip and 3D stacking represents the most promising system integration framework to overcome the communication bottleneck of future many-core processors. From an architecture viewpoint, the availability of an energy-efficient, low-latency bridge connecting the electronic network-on-chip with the optical one is as important as the maturity of the optical interconnect technology. The key design challenge consists of overcoming the inherent serial nature of optical communications, which is typically pursued by increasing either the data rate or the bit-level parallelism, or by a combination thereof. This paper explores an hybrid CMOS-ECL technology platform for bridge implementation by means of a complete logic synthesis effort. By spanning the wider configuration space of the hybrid bridge with respect to fully-CMOS realizations, the paper identifies the most energy-efficient configurations and provides a comparative assessment of achievable quality metrics. Derived results represent a solid and realistic starting point for future optimizations and for the refinement into an actual layout

A Radiation Hardened 16 GS/s Arbitrary Waveform Generator IC for a Submillimeter Wave Chirp-Transform Spectrometer

This paper describes a radiation hardening design approach of a dual channel 16 GSps single chip arbitrary waveform generator (AWG) - a complex mixed-signal ASIC - that consists of a low phase noise 16 GHz PLL, two 1.6 Mbit SRAM blocks, two multiplexing chains, and two 4-bit DACs. The ASIC is dedicated to be a part of a submillimeter wave spectrometer that shall operate in deep-space environment. Under stringent power budget conditions, a selective radiation protection of the ASIC has been applied. The arbitrary waveform generator has been fabricated in a 130 nm SiGe BiCMOS process. Correct functionality has been verified in lab and will be further tested in an irradiation facility

A single chip 16 GS/s arbitrary waveform generator in 0.13 μm BiCMOS technology

This paper presents design considerations and measurements of a dual channel 16 GSps single chip arbitrary waveform generator. Each generator channel consists of a 1.6 Mbit SRAM block, a multiplexing chain, and a 4-bit DAC. A low phase noise 16 GHz PLL is integrated on the same chip. The prototype is designed to perform a lab experiment of a real-time SAW spectrometer. The overall power consumption of the chip is 1.45 W