Testing of Level Shifters in Multiple Voltage Designs

The use of multiple voltages for different cores is becoming a widely accepted technique for efficient power management. Level shifters are used as interfaces between voltage domains. Through extensive transistor level simulations of resistive open, bridging and resistive short faults, we have classified the testing of level shifters into PASSIVE and ACTIVE modes. We examine if high test coverage can be achieved in the PASSIVE mode. We consider resistive opens and shorts and show that, for testing purposes, consideration of purely digital fault effects is sufficient. Thus conventional digital DfT can be employed to test level shifters. In all cases, we conclude that using sets of single supply voltages for testing is sufficient

Dynamic Voltage Scaling Aware Delay Fault Testing

The application of Dynamic Voltage Scaling (DVS) to reduce energy consumption may have a detrimental impact on the quality of manufacturing tests employed to detect permanent faults. This paper analyses the influence of different voltage/frequency settings on fault detection within a DVS application. In particular, the effect of supply voltage on different types of delay faults is considered. This paper presents a study of these problems with simulation results. We have demonstrated that the test application time increases as we reduce the test voltage. We have also shown that for newer technologies we do not have to go to very low voltage levels for delay fault testing. We conclude that it is necessary to test at more than one operating voltage and that the lowest operating voltage does not necessarily give the best fault cover

Printed Circuit Board Fault Inspection Based on Eddy Current Testing Using Planar Coil Sensor

Abstract This paper presents a printed circuit board (PCB) fault inspection method using eddy current testing generated from Helmholtz coils with a planar array-coil sensor to locate and inspect short and open faults on uniformly spaced interconnect single layer PCBs. The differences between the induced voltages from fault-free boards and faulty boards will be recorded in tables and translated into contour plots. The experimental results showed that in the presence of a short fault, the differences between the induced voltages from fault-free and faulty boards are highly negative. However, in the presence of an open fault, the differences between the induced voltages from fault free and faulty boards are highly positive. These highly positive or negative induced voltages can be translated into high density color regions on contour plots. The potential fault positions can be located by observing the color regions of the contour plots with respect to each element of the matrix sensor

A Review on Key Issues and Challenges in Devices Level MEMS Testing

The present review provides information relevant to issues and challenges in MEMS testing techniques that are implemented to analyze the microelectromechanical systems (MEMS) behavior for specific application and operating conditions. MEMS devices are more complex and extremely diverse due to the immersion of multidomains. Their failure modes are distinctive under different circumstances. Therefore, testing of these systems at device level as well as at mass production level, that is, parallel testing, is becoming very challenging as compared to the IC test, because MEMS respond to electrical, physical, chemical, and optical stimuli. Currently, test systems developed for MEMS devices have to be customized due to their nondeterministic behavior and complexity. The accurate measurement of test systems for MEMS is difficult to quantify in the production phase. The complexity of the device to be tested required maturity in the test technique which increases the cost of test development; this practice is directly imposed on the device cost. This factor causes a delay in time-to-market

A Review on Key Issues and Challenges in Devices Level MEMS Testing

The present review provides information relevant to issues and challenges in MEMS testing techniques that are implemented to analyze the microelectromechanical systems (MEMS) behavior for specific application and operating conditions. MEMS devices are more complex and extremely diverse due to the immersion of multidomains. Their failure modes are distinctive under different circumstances. Therefore, testing of these systems at device level as well as at mass production level, that is, parallel testing, is becoming very challenging as compared to the IC test, because MEMS respond to electrical, physical, chemical, and optical stimuli. Currently, test systems developed for MEMS devices have to be customized due to their nondeterministic behavior and complexity. The accurate measurement of test systems for MEMS is difficult to quantify in the production phase. The complexity of the device to be tested required maturity in the test technique which increases the cost of test development; this practice is directly imposed on the device cost. This factor causes a delay in time-to-market

An investigation of delay fault testing for multi voltage design

Multi Voltage Design (MVD) has been successfully applied in contemporary processors as a technique to reduce energy consumption. This work is aimed at finding a generalised delay testing method for MVD. There has been little work to date on testing such systems, but testing the smallest number of operating voltages reduces testing costs. In the initial stage, the impact of varying supply voltage on different types of physical defects is analysed. Simulation results indicate that it is necessary to conduct test at more than one operating voltage and the lowest operating voltage does not necessarily give the best fault coverage. The second part of this work is related to the issues in the testing of level shifters in a MVD environment. The testing of level shifters was analysed to determine if high test coverage can be achieved at a single supply voltage. Resistive opens and shorts were considered and it was shown that, for testing purposes, consideration of purely digital fault effects is sufficient. Multiple faults were also considered. In all cases, it can be concluded that a single supply voltage is sufficient to test the level shifters. To further enhance the quality of test, we have proposed fault modelling and simulations using VHDL-AMS. Our simulation results show that the model derived using simplified VHDL-AMS gives acceptable results and significantly reduces the fault simulations time

Advances in Testing Techniques for Digital Microfluidic Biochips

With the advancement of digital microfluidics technology, applications such as on-chip DNA analysis, point of care diagnosis and automated drug discovery are common nowadays. The use of Digital Microfluidics Biochips (DMFBs) in disease assessment and recognition of target molecules had become popular during the past few years. The reliability of these DMFBs is crucial when they are used in various medical applications. Errors found in these biochips are mainly due to the defects developed during droplet manipulation, chip degradation and inaccuracies in the bio-assay experiments. The recently proposed Micro-electrode-dot Array (MEDA)-based DMFBs involve both fluidic and electronic domains in the micro-electrode cell. Thus, the testing techniques for these biochips should be revised in order to ensure proper functionality. This paper describes recent advances in the testing technologies for digital microfluidics biochips, which would serve as a useful platform for developing revised/new testing techniques for MEDA-based biochips. Therefore, the relevancy of these techniques with respect to testing of MEDA-based biochips is analyzed in order to exploit the full potential of these biochips

A multi-voltage aware resistive open fault model

Resistive open faults (ROFs) represent common interconnect manufacturing defects in VLSI designs {causing delay failures and reliability-related concerns}. The widespread utilization of multiple supply voltages in contemporary VLSI designs and {emerging test methods} poses a critical concern as to whether conventional models for resistive opens will still be effective. Conventional models do not explicitly model the $V_{DD}$ effect on fault behavior and detectability. We have empirically observed that a sensitized ROF could exhibit multiple behaviors across its resistance continuum. We also observed that the detectable resistance range versus $V_{DD}$ varies with test speed. We consequently propose a voltage-aware model which divides the full range of open resistances ($RO$) into continuous behavioral intervals and three detectability ranges.The presented model is expected to substantially enhance multi-voltage test generation and fault distinctio