MachSMT: A Machine Learning-based Algorithm Selector for SMT Solvers

In this paper, we present MachSMT, an algorithm selection tool for state-of-the-art Satisfiability Modulo Theories (SMT) solvers. MachSMT supports the entirety of the logics within the SMT-LIB initiative. MachSMT uses machine learning to learn empirical hardness models (a mapping from SMT-LIB instances to solvers) for state-of-the-art SMT solvers to compute a ranking of which solver is most likely to solve a particular instance the fastest. We analyzed the performance of MachSMT on 102 logics/tracks of SMT-COMP 2019 and observe that it improves on competition winners in 49 logics (with up to 240% in performance for certain logics). MachSMT is clearly not a replacement for any particular SMT solver, but rather a tool that enables users to leverage the collective strength of the diverse set of algorithms implemented as part of these sophisticated solvers. Our MachSMT artifact is available at https://github.com/j29scott/MachSMT

IPASIR-UP: User Propagators for CDCL

Modern SAT solvers are frequently embedded as sub-reasoning engines into more complex tools for addressing problems beyond the Boolean satisfiability problem. Examples include solvers for Satisfiability Modulo Theories (SMT), combinatorial optimization, model enumeration and counting. In such use cases, the SAT solver is often able to provide relevant information beyond the satisfiability answer. Further, domain knowledge of the embedding system (e.g., symmetry properties or theory axioms) can be beneficial for the CDCL search, but cannot be efficiently represented in clausal form. In this paper, we propose a general interface to inspect and influence the internal behaviour of CDCL SAT solvers. Our goal is to capture the most essential functionalities that are sufficient to simplify and improve use cases that require a more fine-grained interaction with the SAT solver than provided via the standard IPASIR interface. For our experiments, we extend CaDiCaL with our interface and evaluate it on two representative use cases: enumerating graphs within the SAT modulo Symmetries framework (SMS), and as the main CDCL(T) SAT engine of the SMT solver cvc5

From Local Search to Quantifier Elimination for Bit-Vectors in SMT

Many applications in hardware and software verification rely on Satisfiability Modulo Theories (SMT) solvers for bit-precise reasoning. For solving quantifier-free bit-vector formulas, current state-of-the-art is a technique called bit-blasting, which eagerly translates a given formula into propositional logic (SAT). Bit-blasting is efficient in practice, but may not scale if the input size can not be reduced sufficiently during preprocessing. For quantified bit-vector logics, the majority of solvers employ instantiation-based techniques, which aim to find conflicting ground instances of quantified formulas. For that, it is crucial to select good instantiations for the universal variables, or else the solver may be overwhelmed by the number of ground instances generated. In this talk I will present a complete propagation-based local search approach for quantifier-free bit-vector formulas. It utilizes conditional inverse value computation on concrete assignments for down-propagation. Computing inverse values of bit-vector operators is not always possible, but we can derive conditions that precisely characterize when bit-vector constraints are invertible. We utilized syntax-guided synthesis techniques to aid in establishing these conditions and verified them independently by using several SMT solvers. I will show how such invertibility conditions can be embedded into quantifier instantiations using Hilbert choice expressions.Non UBCUnreviewedAuthor affiliation: Stanford UniversityPostdoctora

Ternary Propagation-Based Local Search for More Bit-Precise Reasoning

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