Broadband parametric amplification for multiplexed SiMOS quantum dot signals

Spins in semiconductor quantum dots hold great promise as building blocks of quantum processors. Trapping them in SiMOS transistor-like devices eases future industrial scale fabrication. Among the potentially scalable readout solutions, gate-based dispersive radiofrequency reflectometry only requires the already existing transistor gates to readout a quantum dot state, relieving the need for additional elements. In this effort towards scalability, traveling-wave superconducting parametric amplifiers significantly enhance the readout signal-to-noise ratio (SNR) by reducing the noise below typical cryogenic low-noise amplifiers, while offering a broad amplification band, essential to multiplex the readout of multiple resonators. In this work, we demonstrate a 3GHz gate-based reflectometry readout of electron charge states trapped in quantum dots formed in SiMOS multi-gate devices, with SNR enhanced thanks to a Josephson traveling-wave parametric amplifier (JTWPA). The broad, tunable 2GHz amplification bandwidth combined with more than 10dB ON/OFF SNR improvement of the JTWPA enables frequency and time division multiplexed readout of interdot transitions, and noise performance near the quantum limit. In addition, owing to a design without superconducting loops and with a metallic ground plane, the JTWPA is flux insensitive and shows stable performances up to a magnetic field of 1.2T at the quantum dot device, compatible with standard SiMOS spin qubit experiments

Self-Aligned Contacts for the 10nm FDSOI CMOS technology

Dans le cas des générations de transistors sub-14nm, l’intégration de contacts métalliques classiques soumis aux limitations de la lithographie optique ne permet pas d’atteindre les performances d’alignement requises par les règles de dessin (pitch de grille 64nm en FDSOI 10nm) et les rendements industriels. Dans le cadre de ce travail de thèse, une nouvelle architecture de contacts auto-alignés (Self-Aligned Contacts ou SAC) est adressée pour les technologies FDSOI CMOS. Tout d’abord, nous avons proposé et validé l’intégration d’un module SAC dans une route CMOS FDSOI 14nm. Nous avons aussi démontré morphologiquement la faisabilité de contacts SAC pour des pitchs plus agressifs (noeud technologique 10nm). Par le biais de simulations numériques (TCAD et SPICE) l’impact de l’intégration des contacts auto-alignés sur les performances du transistor et du circuit, en termes de capacités parasites notamment, a ensuite été évalué dans le cas de la technologie 10nm FDSOI. Finalement, différentes techniques de transfert de contraintes mécaniques dans le canal du transistor ont été analysées en vue d’améliorer les performances de PFET en 10nm FDSOI. La génération des contraintes mécaniques via les contacts sur source-drain a également été investiguée.For sub-14nm transistor generations, the integration of classical metallic contacts subjected to optical lithography limitations prevents the fulfillment of alignment performance required by design rules (64nm gate pitch for the 10nm node) and industrial yields. In the frame of this PhD. work, an original transistor architecture featuring self-aligned contacts (SAC) is studied for CMOS FDSOI technologies. First, a SAC module has been integrated and validated on a CMOS 14nm FDSOI process flow. The feasibility of SAC integration at a more aggressive gate pitch (10nm node) has also been demonstrated morphologically. The impact of such integration on the transistor and circuit performance, in terms of parasitic capacitances especially, has been evaluated through numerical simulations (TCAD, SPICE) in the case of the 10nm FDSOI technology. Finally, several techniques inducing mechanical stress within the transistor channel have been analyzed in order to improve the device performance. Among those, the use of contacts on source-drain to induce such stress has been particularly investigated

Transistor MOS à espaceurs d'air

n° de priorité : FR20130050941 20130204 ; également publié en tant que : EP2763177 (A1) 2014-08-06 ; US2014217520 (A1) 2014-08-0

Procédé de formation de contacts de grille, de source et de drain sur un transistor MOS

n° de priorité : FR20120054145 2012050

Extra-low parasitic gate-to-contacts capacitance architecture for sub-14 nm transistor nodes

We investigate in this work an original contact architecture to address 64 nm pitch transistor technology. This architecture, studied here in the fully-depleted silicon-on insulator (FDSOI) flavour, remains suitable for planar and 3D (trigate, FinFET) approaches. It includes a recessed gate-first process and self-aligned contacts that offer alternative solutions to technological problems such as limits in lithography resolution and stepper misalignment. Because this type of contact architecture is likely to increase parasitic coupling between gate and source/drain (S/D) contacts, a set of optimization rules is proposed based on numerical simulations. It is found that reducing gate thickness remains the best option to decrease the parasitic gate-to-S/D contact capacitance when transistors feature standard nitride spacers. The use of a low permittivity and thick gate capping layer is highly recommended to limit the sensitivity of parasitic capacitances to non-uniformity associated to chemical mechanical polishing (CMP) and stepper misalignment during S/D contacts lithography. When low-k spacers are considered, the same optimization rules are still relevant to further decrease parasitic capacitances at the transistor level. In the particular case of airgap spacers, they result in a 50% reduction of the total parasitic capacitance. Nevertheless, when used alone, low-k spacers can reduce parasitic coupling by up to 80%; they appear as a first order parameter to tune parasitic capacitances. At the circuit scale, it is demonstrated that an optimized architecture including low-k spacers is mandatory to meet the specific 10 nm node speed requirements at the circuit level. Insights are finally given to correctly choose the active area width W and supply voltage VDD taking into consideration the speed/power consumption trade-off. We particularly showed that if a voltage value lower than the nominal supply voltage is used, spacers optimization become even more effective to reach higher circuit speed at constant dynamic power consumption

Real-time milli-Kelvin thermometry in a semiconductor qubit architecture

International audienceWe report local time-resolved thermometry in a silicon nanowire quantum dot device designed to host a linear array of spin qubits. Using two alternative measurement schemes based on rf reflectometry, we are able to probe either local electron or phonon temperatures with $\mu$s-scale time resolution and a noise equivalent temperature of $3$$\rm mK/\sqrt{\rm Hz}$. Following the application of short microwave pulses, causing local periodic heating, time-dependent thermometry can track the dynamics of thermal excitation and relaxation, revealing clearly different characteristic time scales. This work opens important prospects to investigate the out-of-equilibrium thermal properties of semiconductor quantum electronic devices operating at very low temperature. In particular, it may provide a powerful handle to understand heating effects recently observed in semiconductor spin-qubit systems

Real-time milli-Kelvin thermometry in a semiconductor qubit architecture

International audienceWe report local time-resolved thermometry in a silicon nanowire quantum dot device designed to host a linear array of spin qubits. Using two alternative measurement schemes based on rf reflectometry, we are able to probe either local electron or phonon temperatures with $\mu$s-scale time resolution and a noise equivalent temperature of $3$$\rm mK/\sqrt{\rm Hz}$. Following the application of short microwave pulses, causing local periodic heating, time-dependent thermometry can track the dynamics of thermal excitation and relaxation, revealing clearly different characteristic time scales. This work opens important prospects to investigate the out-of-equilibrium thermal properties of semiconductor quantum electronic devices operating at very low temperature. In particular, it may provide a powerful handle to understand heating effects recently observed in semiconductor spin-qubit systems

Transport characterization of CMOS-based devices fabricated with isotopically-enriched 28Si for spin qubits application

International audienceBoth from a scalability and integration perspective, CMOS-based qubits hold great potential for quantum computing applications. However, current fabrication processes must be adapted to fit qubit requirements, implying a need for controlled process monitoring to compare technological splits as well as to guarantee future process quality. The switch to isotopicallyenriched 28Si as a channel material is one such adaptation that requires deeper study. Here, we fabricate identical devices with 28Si and natural Si and present a comparison of their variabletemperature transport characteristics using the Hall effect and split C-V. Once validated, we use the same 28Si process to fabricate quantum dots which, despite the addition of a second gate level, display state-of-the-art charge noise at 400mK

Strong coupling between a photon and a hole spin in silicon

Spins in semiconductor quantum dots constitute a promising platform for scalable quantum information processing. Coupling them strongly to the photonic modes of superconducting microwave resonators would enable fast non-demolition readout and long-range, on-chip connectivity, well beyond nearest-neighbor quantum interactions. Here we demonstrate strong coupling between a microwave photon in a superconducting resonator and a hole spin in a silicon-based double quantum dot issued from a foundry-compatible MOS fabrication process. By leveraging the strong spin-orbit interaction intrinsically present in the valence band of silicon, we achieve a spin-photon coupling rate as high as 330 MHz largely exceeding the combined spin-photon decoherence rate. This result, together with the recently demonstrated long coherence of hole spins in silicon, opens a new realistic pathway to the development of circuit quantum electrodynamics with spins in semiconductor quantum dots

Strong coupling between a photon and a hole spin in silicon

Spins in semiconductor quantum dots constitute a promising platform for scalable quantum information processing. Coupling them strongly to the photonic modes of superconducting microwave resonators would enable fast non-demolition readout and long-range, on-chip connectivity, well beyond nearest-neighbor quantum interactions. Here we demonstrate strong coupling between a microwave photon in a superconducting resonator and a hole spin in a silicon-based double quantum dot issued from a foundry-compatible MOS fabrication process. By leveraging the strong spin-orbit interaction intrinsically present in the valence band of silicon, we achieve a spin-photon coupling rate as high as 330 MHz largely exceeding the combined spin-photon decoherence rate. This result, together with the recently demonstrated long coherence of hole spins in silicon, opens a new realistic pathway to the development of circuit quantum electrodynamics with spins in semiconductor quantum dots