Heterostructure unipolar spin transistors

We extend the analogy between charge-based bipolar semiconductor electronics and spin-based unipolar electronics by considering unipolar spin transistors with different equilibrium spin splittings in the emitter, base, and collector. The current of base majority spin electrons to the collector limits the performance of ``homojunction'' unipolar spin transistors, in which the emitter, base, and collector all are made from the same magnetic material. This current is very similar in origin to the current of base majority carriers to the emitter in homojunction bipolar junction transistors. The current in bipolar junction transistors can be reduced or nearly eliminated through the use of a wide band gap emitter. We find that the choice of a collector material with a larger equilibrium spin splitting than the base will similarly improve the device performance of a unipolar spin transistor. We also find that a graded variation in the base spin splitting introduces an effective drift field that accelerates minority carriers through the base towards the collector.Comment: 9 pages, 2 figure

Are spin junction transistors suitable for signal processing?

A number of spintronic junction transistors, that exploit the spin degree of freedom of an electron in addition to the charge degree of freedom, have been proposed to provide simultaneous non-volatile storage and signal processing functionality. Here, we show that some of these transistors unfortunately may not have sufficient voltage and current gains for signal processing. This is primarily because of a large output ac conductance and poor isolation between input and output. The latter also hinders unidirectional propagation of logic signal from the input of a logic gate to the output. Other versions of these transistors appear to have better gain and isolation, but not better than those of a conventional transistor. Therefore, these devices may not improve state-of-the-art signal processing capability, although they may provide additional functionality by offering non-volatile storage. They may also have niche applications in non-linear circuits

Evaluation of Silicon Selective Epitaxial Growth Defects using the Sidewall Gate Controlled Diode

Selective Epitaxial Growth (SEG) of silicon has shown great potential for advanced integrated circuit technologies. Before SEG can be fully utilized, sidewall defects must be reduced or at least controlled. The phenomena responsible for these defects were not understood, therefore more quantification of the sidewall defects is necessary. Walled diodes have been used to measure the sidewall leakage currents, but are susceptible to problems which make them poor devices for comparing different sidewall interfaces. A new device structure, the Sidewall Gate Controlled Diode (SGCD), is presented for the quantification of the defects near the SEG sidewall. The SGCD is shown to have advantages over the use of walled diodes despite the complex fabrication process required to build it. The development of the fabrication process for this device and the verification of its useful operation are presented. After the operation of the SGCD was verified, the device was used to evaluate the effects of various SEG deposition parameters on the sidewall defect density. This study determined that lower temperature, slower growth rate depositions followed with an in-situ hydrogen anneal generally reduced the defect density. Inconsistencies in the results also indicated that the profile of the sidewall may also influence the defect density at the SEG/oxide sidewall

Three-Dimensional MOS Process Development

A novel MOS technology for three-dimensional integration of electronic circuits on silicon substrates was developed. Selective epitaxial growth and epitaxial lateral overgrowth of monocrystalline silicon over oxidized silicon were employed to create locally restricted silicon-on-insulator device islands. Thin gate oxides were discovered to deteriorate in ambients typically used for selective epitaxial growth. Conditions of general applicability to silicon epitaxy systems were determined under which this deterioration was greatly reduced. Selective epitaxial growth needed to be carried out at low temperatures. However, crystalline defects increase as deposition temperatures are decreased. An exact dependence between the residual moisture content in epitaxial growth ambients, deposition pressure, and deposition temperature was determined which is also generally applicable to silicon epitaxy systems. The dependences of growth rates and growth rate uniformity on loading, temperature, flow rates, gas composition, and masking oxide thickness were investigated for a pancake type epitaxy reactor. A conceptual model was discussed attempting to describe the effects peculiar to selective epitaxial growth. The newly developed processing steps were assembled to fabricate three dimensional silicon-on-insulator capacitors. These capacitors were electrically evaluated. Surface state densities were in the order of 1O11cm-2 eV-1 and therefore within the range of applicability for a practical CMOS process. Oxidized polysilicon gates were overgrown with silicon by epitaxial lateral overgrowth. The epitaxial silicon was planarized and source and drain regions were formed above the polysilicon gates in Silicon-on-insulator material. The modulation of the source-drain current by bias changes of the buried gate was demonstrated

Amorphous Silicon Thin Film Transistor Fabrication and Models

One of the primary purposes of this research was to develop techniques to improve the quality of vacuum evaporated amorphous silicon (a-Si), i.e. lower the density of localized states in the mobility gap. The electron beam evaporation of amorphouss silicon and hydrogenation by ion implanting has proved promising. This technique permits independent control of amorphous silicon disorder and the hydrogenation level, thereby separating the process of hydrogenation from that of film deposition. Electrical measurement of field effect conductance changes was used as a probing tool to monitor changes in the properties of a-Si before and after hydrogenation. Field effect data was transcribed by a computer program to determine the density of localized states. Amorphous silicon films were prepared by electron beam evaporation of a high purity silicon onto the surface of a thermally oxidized crystalline silicon substrate. The films were deposited at a fixed rate in a high vacuum. Immediately after deposition, some films were subjected to in situ thermal anneal and some films were not. A Comparison of the results of these two eases revealed the porous nature of evaporated a-Si. Hydrogen incorporation into a- Si films was performed by ion implantation followed by a low temperature thermal activation of the hydrogen. After hydrogenation, a field effect conductance change of four orders of magnitude was observed on the devices which were not in situ thermally annealed. A comparison before and after hydrogenation demonstrates that almost three orders of magnitude reduction (from about 1022 to about 1019/cm3-eV) in the density of localized states near the Fermi level (N F/T) was achieved. Varying the hydrogen implantation dosage between lxlO16 to 1.5xl017/cm2, with all other sample preparation procedures fixed, caused a decrease in NF/T from 8.6xl020 to ixl019/cm3-eV. The effect of in situ thermal annealing prior to hydrogen implantation was also investigated. By performing a 400°C anneal for four hours immediately following film deposition the film porosity was greatly reduced. The film was then implanted with hydrogen to a total dose of lxl017/cm2. A field effect Conductance change of six orders of magnitude was observed which yielded a N|F/T of 4xl017/cm3-eV, approaching that of glow discharge produced films. The second purpose of the research was to develop modeling techniques for the a-Si:H TFT. Despite rapid progress in the TFT performence, [performance] the theoretical basis to determine static- and dynamic-characteristics of TFTs has not yet been determined mainly because the influence of the localized states on TFT operation is very complicated. The theoretical expression of drain current as a function of gate bias and drain voltage was derived. To use the theoretical expressions, the localized state density distribution N(E) must be known, A derived yet practical formula for the N(E) did not exist. A common way is to use the experiment of field effect conductance change to determine the N(E), With the data theoretical expressions the localized state density N(E) could be calculated by using a numerical technique, but it is cumbersome and connot [cannot]be determined uniquely. As a design tool for devices and circuits, a simple theory which can express concisely the TFT characteristics is very important. In this report, several models for N(E) are listed:. Approximate analyses for characteristics pf a-Si:H TFT are derived. In two special cases, i.e. uniform localized state density distribution and exponential localized distribution, some useful approximate expressions was obtained. Compared with the experiment data, the uniform density distribution of localized state model is a good approximate expression for a large density discribution [distribution] of localized states near Fermi level. The exponential model is a good approximate expression for lower density distribution of localized states near Fermi level

Local Epitaxial Overgrowth for Stacked Complementary MOS Transistor Pairs

A three-dimensional silicon processing technology for CMOS circuits was developed and characterized. The first fully depleted SOI devices with individually biasable gates on both sides of the silicon film were realized. A vertically stacked CMOS Inverter built by lateral overgrowth was reported for the first time. Nucleation-free epitaxial lateral overgrowth of silicon over thin oxides was developed for both a pancake and a barrel-type epitaxy reactor: This process was optimized to limit damage to gate oxides and minimize dopant diffusion within the Substrate. Autodoping from impurities of the MOS transistors built in the substrate was greatly reduced. A planarisation technique was developed to reduce the silicon film thickness from 13μm to below 0.5μm for full depletion. Chemo-mechanical polishing was modified to yield an automatic etch stop with the corresponding control and uniformity of the silicon film. The resulting wafer topography is more planar than in a conventional substrate CMOS process. PMOS transistors which match the current drive of bulk NM0S devices of equal geometry were characterized, despite the three-times lower hole mobility. Devices realized in the substrate, at the bottom and on top of the SOI film were essentially indistinguishable from bulk devices. A novel device with two insulated gates controlling the same channel was characterized. Inverters were realized both as joint-gate configuration and with symmetric performance of n- and p-channel. These circuits were realized in the area of a single NMOS transistor

Poly silicon Contacted Emitter Bipolar Transistors: Fabrication Development

Traditionally bipolar transistors have monocrystalline emitters that are contacted by metal, usually aluminum. However, the current gain of conventional BJTs does not reach the highest values predicted by theory. This is due to the high doping effects which limit the emitter injection efficiency and/or high minority carrier recombination in the emitter Silicon bipolar technology has reached a state of advancement that the device characteristics and circuit performance are not only determined by the doping profiles but also by the emitter contact technology. In the last few years polycrystalline silicon has been used increasingly as the emitter contacting material. Polysilicon contacted devices have made it possible to achieve much greater emitter injection efficiencies, and possess the ability to greatly increase the current gain a t a given base impurity doping concentration. The performance of bipolar transistors has been considerably enhanced by the use of polysilicon as both a diffusion source and a contact for shallow emitter; devices. Improvements in packing density and switching speed have resulted from the self-aligned structure [2], which has reduced device parasitics, and the lower base current as compared to metal contacted shallow emitter devices. With a lower base current, the base doping level can be increased to reduce the intrinsic base resistance without sacrificing the current gain of the original device [3]. Several researchers have investigated enhanced gains in polysilicon emitter devices, suggested various models to explain their operations, fabricated devices, and obtained good results. However, none of them reported reproducible devices or data from the devices they made in terms of beta variability. The objective of this thesis lies not only in demonstrating that polysilicon emitter transistors have higher current gains than the conventional shallow emitter aluminum contacted devices but also in showing that the polysilicon emitter devices can be manufactured in a consistently reproducible manner. In fabricating n+pn transistors, either arsenic or phosphorus can be used as the dopant for the emitter region in monocrystalline silicon and for the polysilicon contact. Arsenic was chosen for our process due to the superior shallow doping profile that could be obtained. The shallow emitter was formed in the monocrystalline substrate before the polysilicon was deposited on that region to make a polysilicon contact, which is also doped with arsenic. The emitter is then composed of both a monocrystalline and polycrystalline region. The base currents of these shallow emitter devices are controlled by the material, which is polysilicon contacting the emitter, and the interface between the contacting material and the emitter region under the contact. There are three major different theories proposed to explain the improvement in emitter injection efficiency and hence beta of polysilicon contacted transistors. These theories and a model of the conduction mechanisms in polysilicon are discussed in chapter II. Polysilicon emitter contacted bipolar transistors were fabricated by the introduction of two extra masking steps into an existing four mask conventional shallow emitter bipolar process excluding isolation. The basic process and process development are discussed in chapter III. Before devices could be fabricated it was necessary to predict the device performance from the proposed fabrication sequence. The process simulators SUPREM II and SUPREM III have been useful in the design and optimization of integrated circuit technologies. SUPREM II, however, does not model structures that utilize polysilicon. SUPREM III, on the other hand, is an improved process simulator that can model up to five material layers, including polysilicon, and was available in the Engineering Computer Network at Purdue University. Using SUPREM III, the proposed bipolar junction transistor (BJT) structure was modeled and optimized with the existing implants, oxidations, and design rules. The program has predicted that an acceptable profile can be obtained by varying those parameters. This is also included in chapter III. Other processes that were performed for the purpose of developing the polysilicon emitter contacted devices are described. Their characteristics are explained and compared with the test results. Basic electrical measurements were made on both conventional devices and polysilicon emitter contacted devices that were fabricated in the same wafer and conditions except for the polysilicon contact part. Mainly enhanced current gain in the polysilicon emitter contacted devices, the deviation in the current gain values, and resistance values for the contacts over numerous devices are used as the evaluating criteria. The measurement method and results of measurements are discussed in chapter IV. Conclusions and recommendations are made in chapter V

Breakdown Degradation Associated with Elementary Screw Dislocations in 4H-SiC P(+)N Junction Rectifiers

It is well-known that SiC wafer quality deficiencies are delaying the realization of outstandingly superior 4H-SiC power electronics. While efforts to date have centered on eradicating micropipes (i.e., hollow core super-screw dislocations with Burgers vector greater than 2c), 4H-SiC wafers and epilayers also contain elementary screw dislocations (i.e., Burgers vector = lc with no hollow core) in densities on the order of thousands per sq cm, nearly 100-fold micropipe densities. This paper describes an initial study into the impact of elementary screw dislocations on the reverse-bias current-voltage (I-V) characteristics of 4H-SiC p(+)n diodes. First, Synchrotron White Beam X-ray Topography (SWBXT) was employed to map the exact locations of elementary screw dislocations within small-area 4H-SiC p(+)n mesa diodes. Then the high-field reverse leakage and breakdown properties of these diodes were subsequently characterized on a probing station outfitted with a dark box and video camera. Most devices without screw dislocations exhibited excellent characteristics, with no detectable leakage current prior to breakdown, a sharp breakdown I-V knee, and no visible concentration of breakdown current. In contrast devices that contained at least one elementary screw dislocation exhibited a 5% to 35% reduction in breakdown voltage, a softer breakdown I-V knee, and visible microplasmas in which highly localized breakdown current was concentrated. The locations of observed breakdown microplasmas corresponded exactly to the locations of elementary screw dislocations identified by SWBXT mapping. While not as detrimental to SiC device performance as micropipes, the undesirable breakdown characteristics of elementary screw dislocations could nevertheless adversely affect the performance and reliability of 4H-SiC power devices

Surface and Interface Properties of PdCr/SiC Schottky Diode Gas Sensor Annealed at 425 C

The surface and interface properties of Pd(0.9)Cr(0.1)/SiC Schottky diode gas sensors both before and after annealing are investigated using Auger Electron Spectroscopy (AES), Scanning Electron Microscopy (SEM), and Energy Dispersive Spectroscopy (EDS). At room temperature the alloy reacted with SiC and formed Pd(x)Si only in a very narrow interfacial region. After annealing for 250 hours at 425 C, the surface of the Schottky contact area has much less silicon and carbon contamination than that found on the surface of an annealed Pd/SiC structure. Palladium silicides (Pd(x)Si) formed at a broadened interface after annealing, but a significant layer of alloy film is still free of silicon and carbon. The chromium concentration with respect to palladium is quite uniform down to the deep interface region. A stable catalytic surface and a clean layer of Pd(0.9)Cr(0.1) film are likely responsible for significantly improved device sensitivity