Automist - A Tool for Automated Instruction Set Characterization of Embedded Processors

The steadily increasing performance of mobile devices also implies a rise in power consumption. To counteract this trend it is mandatory to accomplish software power optimizations based on accurate power consumption models characterized for the processor. This paper presents an environment for automated instruction set characterization based on physical power measurements. Based on a detailed instruction set description a testbench generator creates all needed test programs for a complete characterization. Afterwards those programs are executed by the processor and the energy consumption is measured. For an accurate energy measurement a high performance sampling technique has been established, which can be either clock or energy driven

Methodologies for Designing Power-Aware Smart Card Systems

Smart cards are some of the smallest computing platforms in use today. They have limited resources, but a huge number of functional requirements. The requirement for multi-application cards increases the demand for high performance and security even more, whereas the limits given by size and energy consumption remain constant. We describe new methodologies for designing and implementing entire systems with regard to power awareness and required performance. To make use of this power-saving potential, also the higher layers of the system - the operating system layer and the application domain layer - are required to be designed together with the rest of the system. HW/SW co-design methodologies enable the gain of system-level optimization. The first part presents the abstraction of smart cards to optimize system architecture and memory system. Both functional and transactional-level models are presented and discussed. The proposed design flow and preliminary results of the evaluation are depicted. Another central part of this methodology is a cycle-accurate instruction-set simulator for secure software development. The underlaying energy model is designed to decouple instruction and data dependent energy dissipation, which leads to an independent characterization process and allows stepwise model refinement to increase estimation accuracy. The model has been evaluated for a high-performance smart card CPU and an use-case for secure software is given

Compiler-based Software Power Peak Elimination on Smart Card Systems

RF-powered smart cards are widely used in different application areas today. For smart cards not only performance is an important attribute, but also the power consumed by a given application. The power consumed is heavily depending on the software executed on the system. The power profile, especially the power peaks, of an executed application influence the system stability and security. Flattening the power profile can thus increase the stability and security of a system. In this paper we present an optimization system that allows a reduction of power peaks based on a compiler optimization. The optimizations are done on different levels of the compiler. In the backend of the compiler we present new instruction scheduling algorithms. On the intermediate language level we propose the use of iterative compiling for reducing critical peaks

Automist- A Tool for Automated Instruction Set Characterization of Embedded Processors

Abstract. The steadily increasing performance of mobile devices also implies a rise in power consumption. To counteract this trend it is mandatory to accomplish software power optimizations based on accurate power consumption models characterized for the processor. This paper presents an environment for automated instruction set characterization based on physical power measurements. Based on a detailed instruction set description a testbench generator creates all needed test programs for a complete characterization. Afterwards those programs are executed by the processor and the energy consumption is measured. For an accurate energy measurement a high performance sampling technique has been established, which can be either clock or energy driven

Polydepsipeptide Block-Stabilized Polyplexes for Efficient Transfection of Primary Human Cells

The rational design of a polyplex gene carrier aims to balance maximal effectiveness of nucleic acid transfection into cells with minimal adverse effects. Depsipeptide blocks with an <i>M</i>_n ∼ 5 kDa exhibiting strong physical interactions were conjugated with PEI moieties (2.5 or 10 kDa) to di- and triblock copolymers. Upon nanoparticle formation and complexation with DNA, the resulting polyplexes (sizes typically 60–150 nm) showed remarkable stability compared to PEI-only or lipoplex and facilitated efficient gene delivery. Intracellular trafficking was visualized by observing fluorescence-labeled pDNA and highlighted the effective cytoplasmic uptake of polyplexes and release of DNA to the perinuclear space. Specifically, a triblock copolymer with a middle depsipeptide block and two 10 kDa PEI swallowtail structures mediated the highest levels of transgenic VEGF secretion in mesenchymal stem cells with low cytotoxicity. These nanocarriers form the basis for a delivery platform technology, especially for gene transfer to primary human cells