Modeling with SpecCharts

SpecCharts is a language intended for system level description and synthesis. It is based on hierarchical state diagrams, posseses many constructs designed to facilitate ease of system level descriptions, and is simulatable via a translator from SpecCharts to VHDL. To test the feasability of using the language, several examples were modeled using SpecCharts, were converted to VHDL, and simulated to verify correctness. The details of two of those examples are provided in this report

System clock estimation based on clock wastage minimization

When synthesizing a hardware implementation from behavioral descriptions, an important decision is the selection of a clock cycle to schedule the datapath operations into control steps. Most existing behavioral synthesis systems either require the designer to specify the clock cycle explicitly or require that the delays of the operators used in the design be specified in multiples of a clock cycle. In the absence of any tool to guide the selection of a clock cycle, a bad choice of the clock period could adversely affect the performance of the synthesized design. We present an algorithm for estimating the system clock based on a clock wastage minimization criteria. Limitations of previous approaches to the problem are discussed. The results obtained prove that the clock cycle estimated by the Clock Wastage Minimization method produce faster designs than previous solutions to the problem

Synthesis from specifications : basic concepts

The need has evolved for a synthesis tool at the computer system level. SpecSyn is one such tool. Basically, it will view the world as a set of chips communicating via protocols. Thus, an abstract specification would get synthesized into a set of one or more interconnected chips. From that point, detail is added to each chip's specification until its structure is synthesized or it is determined that a prefabricated chip similar in functionality can be used.Features of such a tool include executable specifications from which to synthesize, constraint driven partitioning of the specifications into components (chips) and synthesis of interfaces between them, translation into VHDL and synthesis into VHDL structures of micro-architectural components, and the use of other tools (e.g. MILO, a micro-architecture and logic optimizer, and LES, a layout expert system) to evaluate the quality of the chip layout generated from VHDL description.A major component of SpecSyn is SpecCharts, a high level specification language amenable to system level synthesis, able to represent designs from system to register transfer levels. The language consists of a hierarchy of states, represented in combined graphical and textual form, at the same time catering to the expression of concurrent behavior and specification of constraints. With it we have specified several Intel chips as well as higher level systems, and have found it to be quite powerful and easy to use.SpecSyn will have a graphical interface, from which the user can at any time view or edit a SpecChart, translate to VHDL and simulate, view statistics provided by estimators (such as area, speed, and pins), store and retrieve SpecCharts, apply basic Spec Chart operations, as well as apply the partitioning algorithms or interface synthesizer. Providing access to a wide range of tools, having a single language represent the design throughout the synthesis process, and having user specified constraints allow the user to have varying amounts of control over the synthesis process

Constant-time cost evaluation for behavioral partitioning

Given a system behavioral specification, partitioning can be used to distribute among chips the processes, procedures, and storage elements that comprise the specification. We introduce a technique for constant-time recomputation of pin, area, and execution-time estimates for a behavioral partitioning move. The technique permits fast, accurate estimations of a large number of partitionings, thus enabling better results than approaches which attain tractable computation time by using gross estimates or less thorough partitioning algorithms. The key to our technique is the isolation and extraction before partitioning of the basic design attributes needed for estimation, and the updating of this information in constant-time for each move. The estimation models are almost as detailed as those presented in previous estimation approaches not intended for constant-time update. The results we provide indicate the speed and practicality of our estimation approach in conjunction with sophisticated partitioning algorithms

Incorporating VHDL signal/wait semantics into synthesis

VHDL signals and wait statements provide great expressive power for behavioral descriptions. However, due to their simulation semantics, most high-level synthesis tools do not handle these constructs and severely restrict their use, eliminating much of their power. In this report, we introduce a set of transformations to convert signals and wait statements to equivalent constructs that are easily handled by high-level synthesis tools. They greatly enlarge the synthesizable VHDL subset, thus increasing the usefulness and practicality of the language as an input to high-level synthesis. These transformations can also serve as a basis for converting a VHDL process to a form suitable for generation of software

Semantics and synthesis of signals in behavioral VHDL

Signals are a fundamental part of VHDL behavioral descriptions. There are many kinds of VHDL signals, each possesing complex and hence often misunderstood semantics. The result is that synthesis tools often inadequately address synthesis of signals. In this report, we first make clear the semantics of the various signal kinds shared by multiple processes through the use of conceptual hardware, rather than just text. Second, with the semantics firmly understood, we discuss techniques and issues in synthesizing actual hardware for shared signals. This information can be used to take a step towards synthesizing correct hardware from VHDL descriptions while greatly reducing current restrictions imposed by synthesis tools on allowable VHDL behavior

SpecCharts : a language for system level specification and synthesis

SpecCharts is a new language intended for system level specification and synthesis. SpecCharts represent a multi-module system with a hierarchy of state diagrams, catering to the expression of concurrent behavior, and using VHDL sequential statement semantics to describe a leaf state's (a state not composed of substates) functionality. The language permits protocol based data transfer, estimations, constraints, and state based description, all of which enable the omission of detail and thus enhance the comprehension of a system's behavior. The language is intended to represent a design throughout the system and chip levels of synthesis. i.e. converting an abstract specification into a set of one or more interconnected chips/modules, each having a well defined structure or being bound to a prefabricated component. Since good system design requires an executable specification language, SpecCharts can be simulated via automatic conversion to VHDL

Rhythm Control in Heart Failure Patients With Atrial Fibrillation Contemporary Challenges Including the Role of Ablation

AbstractBecause nonpharmacological interventions likely alter the risks and benefits associated with rhythm control, this paper reviews the role of current rhythm control strategies in atrial fibrillation. This report also focuses on the specific limitations of pharmacological interventions and the utility of percutaneous ablation in this growing population of patients with concomitant atrial fibrillation and heart failure

Ventricular Arrhythmia Discriminator Programming and the Impact on the Incidence of Inappropriate Therapy in Patients with Implantable Cardiac Defibrillators

Background: The incidence of inappropriate therapy from implantable cardioverter defibrillators (ICDs) has been reduced by programming ventricular arrhythmia discriminators (VAD) on at the time of implant. Objective: To determine which VAD is most effective in preventing inappropriate therapy.Methods and Results: Dual chamber ICD (n=48) or cardiac resynchronization therapy defibrillator (CRT-D) (n=55) implantation was performed in 103 patients (M=94, F=9). Patients were followed prospectively for therapy events (shock or anti-tachycardia pacing) for a mean 362±289 days. Events were correlated with clinical characteristics and VAD programming. Of the 103 pts followed, 11 received inappropriate therapy (IT), 15 received appropriate therapy (AT), and 77 received no therapy (NT). In the AT and IT groups, a total of 207 events (ATP=171, shock=36) were observed. A total of sixty-four electrograms (EGMs) were analyzed. Programming VADs "ON" versus "OFF" reduced the incidence of IT events compared to those receiving AT or NT events (p<.01), with a trend in fewer patients receiving IT (31.3% "ON" vs 55.6% "OFF", p = 0.131). Programming atrial fibrillation (AF) detection ON resulted in fewer patients receiving IT compared to those receiving AT or NT (3.6% vs 19%, p<.05). Furthermore, programming AF or AFL algorithms "ON", resulted in overall fewer episodes of IT therapy (p<.01). Conclusions: AF or AFL discriminators significantly reduced the incidence of IT, and were predominantly responsible for the benefits from VAD programming observed in this study. Activating these features as part of routine ICD or CRT-D programming may provide a simple and effective alternative to the use of more complex and multiple VAD strategies

Predicting acute termination and non-termination during ablation of human atrial fibrillation using quantitative indices

Background: Termination of atrial fibrillation (AF), the most common arrhythmia in the United States, during catheter ablation is an attractive procedural endpoint, which has been associated with improved long-term outcome in some studies. It is not clear, however, whether it is possible to predict termination using clinical data. We developed and applied three quantitative indices in global multielectrode recordings of AF prior to ablation: average dominant frequency (ADF), spectral power index (SPI), and electrogram quality index (EQI). Methods: In N = 42 persistent AF patients (65 ± 9 years, 14% female) we collected unipolar electrograms from 64-pole baskets (Abbott, CA). We studied N = 17 patients in whom AF terminated during ablation ('Term') and N = 25 in whom it did not ('Non-term'). For each index, we determined its ability to predict ablation by computing receiver operating characteristic (ROC) and calculated the area under the curve (AUC). Results: The ADF did not differ for Term and Non-term patients at 5.28 ± 0.82 Hz and 5.51 ± 0.81 Hz, respectively (p = 0.34). Conversely, the SPI for these two groups was. 0.85 (0.80-0.92) and 0.97 (0.93-0.98) and the EQI was 0.61 (0.58-0.64) and 0.56 (0.55-0.59) (p < 0.0001). The AUC for predicting AF termination for the SPI was 0.85 ([0.68, 0.95] 95% CI), and for the EQI, 0.86 ([0.72, 0.95] 95% CI). Conclusion: Both the EQI and the SPI may provide a useful clinical tool to predict procedural ablation outcome in persistent AF patients. Future studies are required to identify which physiological features of AF are revealed by these indices and hence linked to AF termination or non-termination