Towards prevention of sportsmen burnout : Formal analysis of sub-optimal tournament scheduling

Funding Statement: The authors are grateful to the Deanship of Scientific Research at King Saud University, Saudi Arabia for funding this work through the Vice Deanship of Scientific Research Chairs: Chair of Pervasive and Mobile Computing.Peer reviewedPublisher PD

Environment Friendly Energy Cooperation in Neighboring Buildings : A Transformed Linearization Approach

Funding Information: Funding: This work was supported in part by the National Research Foundation of Korea-Grant funded by the Korean Government (Ministry of Science and ICT) under Grant NRF-2020R1A2B5B02002478, and in part by the Sejong University Research Faculty Program (20212023). Publisher Copyright: © 2022 by the authors. Licensee MDPI, Basel, Switzerland.Peer reviewedPublisher PD

A Non-Blocking Fault-Tolerant Asynchronous Network-on-Chip Router

Abweichender Titel laut Übersetzung der Verfasserin/des VerfassersZsfassung in dt. SpracheDie Gesamtleistung der heutigen komplexen Systems-on-Chip (SoCs) wird entscheidend durch die Leistungsfähigkeit der Networks-on-Chip (NoCs) bestimmt. Die zunehmende Verkleinerung der Halbleiter-Strukturgrößen ermöglicht hier zwar immer höhere Taktraten, stellt jedoch gleichzeitig das übliche global synchrone Paradigma vor wachsende Herausforderungen. Hierzu zählt die Verteilung des Taktsignals über den gesamten Chip ebenso wie die Beherrschung der signifikanten Variationen der Signallaufzeiten. Im Gegensatz dazu basieren asynchrone Schaltungen auf Handshakes, womit sie Probleme mit dem Takt elegant vermeiden. Gleichzeitig erlauben sie einen effizienten Umgang mit Prozessvariationen und sogar dynamisch auftretenden Veränderungen von Laufzeitparametern. Das Interesse an asynchronen Schaltungen nimmt daher stark zu, und auch wir konzentrieren uns in dieser Arbeit auf asynchrone NoCs. Ein entscheidender Vorteil von NoCs gegenüber traditionellen Busstrukturen ist ihre Fähigkeit, über verschiedene Pfade parallel Nachrichten zu übertragen. Das Blockieren eines Pfades ist in diesem Kontext unerwünscht, da es mit gravierenden Leistungseinbußen und dem Verlust der Echtzeitfähigkeit verbunden ist. Demgemäß beschäftigt sich die Literatur auch ausführlich mit nicht-blockierendem Verhalten, allerdings nicht immer in korrekter Weise. So konnten wir zeigen, dass einige existierende Lösungen einen sicheren Datenaustausch nicht immer garantieren können. Ein Ergebnis unserer Arbeit ist daher ein Framework, welches notwendige Bedingungen zur Konstruktion eines nicht-blockierenden NoCs definiert. Wir zeigen die Korrektheit unseres Frameworks anhand des Entwurfes eines neuen NoC Protokolls, welches nicht nur alle funktionalen Anforderungen erfüllt, sondern auch den Leistungsverbrauch auf langen Verbindungen reduziert und die Anforderungen an die Bandbreite lockert. Eine weitere Folge der Miniaturisierung ist eine erhöhte Anfälligkeit von Chips gegenüber transienten Fehlern. Ursache dafür sind kleinere Transistor-Geometrien sowie niedrigere Spannungspegel, was zu geringeren kritischen Ladungen führt. Dem entsprechend wächst auch die Bedeutung von Fehlertoleranz. Asynchrone NoCs enthalten allerdings einige Komponenten, für welche die konventionelle Fehlertoleranzmethode der Replikation nicht bzw. nicht effizient eingesetzt werden kann. Ein Beispiel hierfür sind Arbiter, die auf nicht deterministische Weise den Zugriff auf geteilte Ressourcen regeln. Das zweite wesentliche Ergebnis dieser Arbeit ist daher der systematische Schutz einiger dieser Komponenten, insbesondere eines Arbiters, vor transienten Fehlern. Außerdem präsentieren wir das Design eines vollständigen fehlertoleranten Routers, welcher zudem einen hochperformantenArbiter enthält. Zur Evaluierung unseres Designs verwenden wir funktionale Verifikation anhand von teilautomatisierten post-layout Simulationen, gepaart mit formaler Verifikation mittels Model Checking.It is well understood that the throughput of Networks-on-Chip (NoCs) is decisive for the performance of today's complex Systems-on-Chip (SoCs). On the one hand, proceeding miniaturization has allowed these systems to operate at ever increasing clock rates, on the other hand, however, the globally synchronous designs face certain challenges that are difficult to overcome for recent technology nodes. This includes the distribution of clocks across a complete chip, and robustness against delay variations. The handshake based style of control flow in asynchronous communication style naturally eliminates the need for a global clock, and at the same time provides an inherent ability to adapt to uncertainties and even dynamic changes of timing parameters. Because of these reasons, they are receiving increasing attention in the embedded systems community, and for the same reason we will also concentrate on asynchronous NoCs in this work. A crucial advantage of NoCs over traditional bus structures is the ability to perform several independent message transfers in parallel, namely along different routes. In this situation blocking of a link is highly undesired, as it severely degrades performance and real time capabilities of a NoC. A very important property of a NoC is therefore non-blocking behavior. The latter is widely addressed in literature, but unfortunately not always correctly understood and presented. We will show that a few existing solutions do not guarantee a safe data exchange between two communicating entities. One contribution of our work, therefore, is to present a framework that precisely elaborates the minimum requirements of building a nonblocking NoC.We also demonstrate the correctness of our framework by proposing a novel solution that not just satisfies all the functional requirements, but reduces the power consumption on long interconnects, and relaxes the bandwidth requirements. Another undesired consequence of the miniaturization process is the higher susceptibility of VLSI circuits to transient faults, which is due to the smaller geometries and lower supply voltages which in turn reduce the critical charge. Fault tolerance is therefore predicted to become a crucial property in context with future technologies. As far as asynchronous NoCs are concerned, they comprise several such circuits that cannot be made fault-tolerant by using conventional replication techniques. One such circuit is an arbiter that allows resource sharing in a nondeterministic manner. Therefore the second major contribution of this work is to systematically harden a few of those circuits, including an arbiter cell. Other than these, we also present the design of a complete fault-tolerant asynchronous router, which in addition promises high speed resource sharing capability. Our evaluation is partially supported with formal verification using model checking, and partially using post layout functional verification based on Modelsim scripts.16

Prediction of Critical Currents for a Diluted Square Lattice Using Artificial Neural Networks

Studying critical currents, critical temperatures, and critical fields carries substantial importance in the field of superconductivity. In this work, we study critical currents in the current–voltage characteristics of a diluted-square lattice on an Nb film. Our measurements are based on a commercially available Physical Properties Measurement System, which may prove time consuming and costly for repeated measurements for a wide range of parameters. We therefore propose a technique based on artificial neural networks to facilitate extrapolation of these curves for unforeseen values of temperature and magnetic fields. We demonstrate that our proposed algorithm predicts the curves with an immaculate precision and minimal overhead, which may as well be adopted for prediction in other types of regular and diluted lattices. In addition, we present a detailed comparison between three artificial neural networks architectures with respect to their prediction efficiency, computation time, and number of iterations to converge to an optimal solution

Formal Verification of Hardware Components in Critical Systems

Hardware components, such as memory and arithmetic units, are integral part of every computer-controlled system, for example, Unmanned Aerial Vehicles (UAVs). The fundamental requirement of these hardware components is that they must behave as desired; otherwise, the whole system built upon them may fail. To determine whether or not a component is behaving adequately, the desired behaviour of the component is often specified in the Boolean algebra. Boolean algebra is one of the most widely used mathematical tools to analyse hardware components represented at gate level using Boolean functions. To ensure reliable computer-controlled system design, simulation and testing methods are commonly used to detect faults; however, such methods do not ensure absence of faults. In critical systems’ design, such as UAVs, the simulation-based techniques are often augmented with mathematical tools and techniques to prove stronger properties, for example, absence of faults, in the early stages of the system design. In this paper, we define a lightweight mathematical framework in computer-based theorem prover Coq for describing and reasoning about Boolean algebra and hardware components (logic circuits) modelled as Boolean functions. To demonstrate the usefulness of the framework, we (1) define and prove the correctness of principle of duality mechanically using a computer tool and all basic theorems of Boolean algebra, (2) formally define the algebraic manipulation (step-by-step procedure of proving functional equivalence of functions) used in Boolean function simplification, and (3) verify functional correctness and reliability properties of two hardware components. The major advantage of using mechanical theorem provers is that the correctness of all definitions and proofs can be checked mechanically using the type checker and proof checker facilities of the proof assistant Coq

Reversible integer wavelet transform for blind image hiding method

<div><p>In this article, a blind data hiding reversible methodology to embed the secret data for hiding purpose into cover image is proposed. The key advantage of this research work is to resolve the privacy and secrecy issues raised during the data transmission over the internet. Firstly, data is decomposed into sub-bands using the integer wavelets. For decomposition, the Fresnelet transform is utilized which encrypts the secret data by choosing a unique key parameter to construct a dummy pattern. The dummy pattern is then embedded into an approximated sub-band of the cover image. Our proposed method reveals high-capacity and great imperceptibility of the secret embedded data. With the utilization of family of integer wavelets, the proposed novel approach becomes more efficient for hiding and retrieving process. It retrieved the secret hidden data from the embedded data blindly, without the requirement of original cover image.</p></div

A novel framework for approximating resistance–temperature characteristics of a superconducting film based on artificial neural networks

Funding Information: The authors are grateful to the Deanship of Scientific Research at King Saud University , Saudi Arabia for funding this work through the Vice Deanship of Scientific Research Chairs: Chair of Pervasive and Mobile Computing. Publisher Copyright: © 2021 The AuthorsPeer reviewedPublisher PD

Nomenclature.

<p>Nomenclature.</p

Graphical demonstration of the comparison of Table 4.

<p>(A) Capacity carried by Lena, (B) capacity carried by Airplane, (C) capacity carried by Boat, and (D) capacity carried by Mandrill. (Images information is given in Data Availability Statement.)</p