A 1,000 Frames/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors

A programmable vision chip with variable resolution and row-pixel-mixed parallel image processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale image processors, pixel-parallel SIMD Processing Element (PE) array, and instruction controller. The resolution of the image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level image processing and sends out features of the image for various applications. It can perform image processing at over 1,000 frames/s (fps). A prototype chip with 64 × 64 pixels resolution and 6-bit gray-scale image is fabricated in 0.18 μm Standard CMOS process. The area size of chip is 1.5 mm × 3.5 mm. Each pixel size is 9.5 μm × 9.5 μm and each processing element size is 23 μm × 29 μm. The experiment results demonstrate that the chip can perform low-level and mid-level image processing and it can be applied in the real-time vision applications, such as high speed target tracking

High speed CMOS vision chips

This paper presents novel high speed vision chips based on multiple levels of parallel processors. The chip integrates CMOS image sensor, multiple-levels of SIMD parallel processors and an embedded microprocessor unit. The multiple-levels of SIMD parallel processors consist of an array processor of SIMD processing elements(PEs) and a column of SIMD row processors(RPs). The PE array and RPs have an O(NxN) parallelism and an O(N) parallelism, respectively. The PE array, RPs and MPU can execute low-, mid- and high-level image processing algorithms, respectively. Prototype chips are fabricated using the0.18μm CMOS process. Applications including target tracking, pattern extraction and image recognition are demonstrated.?2011 IEEE

An ultra-low-power RF transceiver for WBANs in medical applications

A2.4 GHz ultra-low-power RF transceiver with a900 MHz auxiliary wake-up link for wireless body area networks(WBANs) in medical applications is presented. The RF transceiver with an asymmetric architecture is proposed to achieve high energy efficiency according to the asymmetric communication in WBANs. The transceiver consists of a main receiver(RX) with an ultra-low-power free-running ring oscillator and a high speed main transmitter(TX) with fast lock-in PLL. A passive wake-up receiver(WuRx) for wake-up function with a high power conversion efficiency(PCE) CMOS rectifier is designed to offer the sensor node the capability of work-on-demand with zero standby power. The chip is implemented in a0.18μm CMOS process. Its core area is1.6 mm2. The main RX achieves a sensitivity of-55 dBm at a100 kbps OOK data rate while consuming just210μA current from the1 V power supply. The main TX achieves+3 dBm output power with a4 Mbps/500 kbps/200 kbps data rate for OOK/4 FSK/2 FSK modulation and dissipates3.25 mA/6.5 mA/6.5 mA current from a1.8 V power supply. The minimum detectable RF input energy for the wake-up RX is-15 dBm and the PCE is more than25%.?2011 Chinese Institute of Electronics

A passive UHF RFID tag chip with a dual-resolution temperature sensor in a0.18μm standard CMOS process

This paper presents a passive EPC Gen-2 UHF RFID tag chip with a dual-resolution temperature sensor. The chip tag integrates a temperature sensor, an RF/analog front-end circuit, an NVM memory and a digital baseband in a standard CMOS process. The sensor with a low power sigma- delta(ΣΔ) ADC is designed to operate in low and high resolution modes. It can not only achieve the target accuracy but also reduce the power consumption and the sensing time. A CMOS-only RF rectifier and a single-poly non-volatile memory(NVM) are designed to realize a low cost tag chip. The192-bit-NVM tag chip with an area of1 mm2 is implemented in a0.18-μm standard CMOS process. The sensitivity of the tag is-10.7 dBm/-8.4 dBm when the sensor is disabled/enabled. It achieves a maximum reading/sensing distance of4 m/3.1 m at2 W EIRP. The inaccuracy of the sensor is-0.6°C/0.5°C(-1.0°C/1.2°C) in the operating range from5 to15°C in high resolution mode(-30 to50°C in low resolution mode). The resolution of the sensor achieves0.02°C(0.18°C) in high(low) resolution mode.?2011 Chinese Institute of Electronics

A fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system in0.13μm CMOS

This paper proposes a sigma- delta fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system. With reasonable frequency planning, the system can be used in multi-standard wireless communication applications(GSM, WCDMA, GPRS, TD-SCDMA, WLAN(802.11a/b/g)). The implementation is achieved by a0.13μm RF CMOS process. The measured results demonstrate that three quadrature VCOs(QVCO) continuously cover the frequency from3.1 to6.1 GHz(65.2%), and through the successive divide-by-2 prescalers to achieve the frequency from0.75 to6.1 GHz continuously. The chip was fully integrated with the exception of an off-chip filter. The entire chip area is only3.78 mm2, and the system consumes a21.7 [email protected] V supply without output buffers. The lock-in time of the PLL frequency synthesizer is less than4μs over the entire frequency range with a direct frequency presetting technique and the auxiliary non-volatile memory(NVM) can store the digital configuration signal of the system, including presetting signals to avoid the calibration process case by case.?2011 Chinese Institute of Electronics

A Hybrid Random Number Generator Using Single Electron Tunneling Junctions and MOS Transistors

This paper proposes a novel single electron random number generator (RNG). The generator consists of multiple tunneling junctions (MTJ) and a hybrid single electron transistor (SET)/MOS output circuit. It is an oscillator-based RNG. MTJ is used to implement a high-frequency oscillator,which uses the inherent physical randomness in tunneling events of the MTJ to achieve large frequency drift. The hybrid SET and MOS output circuit is used to amplify and buffer the output signal of the MTJ oscillator. The RNG circuit generates high-quality random digital sequences with a simple structure. The operation speed of this circuit is as high as 1GHz. The circuit also has good driven capability and low power dissipation. This novel random number generator is a promising device for future cryptographic systems and communication applications

A Low-Cost CMOS Programmable Temperature Switch

A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature Tth can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature Tth variation that results form the process tolerance. The switch circuit is implemented in a standard 0.35 μm CMOS process. The temperature switch can be programmed to perform the switch operation at 16 different threshold temperature Tths from 45ï¼Â120°C with a 5°C increment. The measurement shows a good consistency in the threshold temperatures. The chip core area is 0.04 mm2 and power consumption is 3.1 μA at 3.3V power supply. The advantages of the temperature switch are low power consumption, the programmable threshold temperature and the controllable hysteresis

A Novel 4T nMOS-Only SRAM Cell in 32nm Technology Node

This paper proposes a novel loadless 4T SRAM cell composed of nMOS transistors. The SRAM cell is based on 32nm silicon-on-insulator （SO1） technology node. It consists of two access transistors and two pull-down transistors. The pull-down transistors have larger channel length than the access transistors. Due to the significant short channel effect of small-size MOS transistors, the access transistors have much larger leakage current than the pull-down transistors,enabling the SRAM cell to maintain logic ＂1＂ while in standby. The storage node voltages of the cell are fed back to the back-gates of the access transistors,enabling the stable ＂read＂ operation of the cell. The use of back-gate feedback also helps to im- prove the static noise margin （SNM） of the cell. The proposed SRAM cell has smaller area than conventional bulk 6T SRAM cells and 4T SRAM cells. The speed and power dissipation of the SRAM cell are simulated and discussed. The SRAM cell can operate with a 0. 5V supply voltage