43 research outputs found

    Simultaneous enlargement of SRAM read/write noise margin by controlling virtual ground lines

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    金沢大学理工研究域電子情報学系The SRAM operating margin in 65nm technology is analyzed. The peak characteristic in the read margin versus the supply voltage was found to be caused by the channel length modulation effect. Controlling the memory cell virtual ground line proved to be effective in enlarging the operating margin simultaneously in the read and the write operations. A simple o ptimum circuit which does not require any dynamic voltage c ontrol is proposed, realizing an improvement in the operating m argin comparable to conventional circuits requiring dynamic voltage control. © 2010 IEEE

    Accelerated evaluation method for the SRAM cell write margin using word line voltage shift

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    An accelerated evaluation method for the SRAM cell write margin is proposed based on the conventional Write Noise Margin (WNM) definition. The WNM is measured under a lower word line voltage than the power supply voltage VDD. A lower word line voltage is used because the access transistor operates in the saturation mode over a wide range of threshold voltage variation. The final WNM at the VDD word line voltage, the Accelerated Write Noise Margin (AWNM), is obtained by shifting the measured WNM at the lower word line voltage. The amount of WNM shift is determined from the WNM dependence on the word line voltage. As a result, the cumulative frequency of the AWNM displays a normal distribution. A normal distribution of the AWNM drastically improves development efficiency, because the write failure probability can be estimated by a small number of samples. Effectiveness of the proposed method is verified using the Monte Carlo simulation. © 2011 IEEE

    White Paper from Workshop on Large-scale Parallel Numerical Computing Technology (LSPANC 2020): HPC and Computer Arithmetic toward Minimal-Precision Computing

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    In numerical computations, precision of floating-point computations is a key factor to determine the performance (speed and energy-efficiency) as well as the reliability (accuracy and reproducibility). However, precision generally plays a contrary role for both. Therefore, the ultimate concept for maximizing both at the same time is the minimal-precision computing through precision-tuning, which adjusts the optimal precision for each operation and data. Several studies have been already conducted for it so far (e.g. Precimoniuos and Verrou), but the scope of those studies is limited to the precision-tuning alone. Hence, we aim to propose a broader concept of the minimal-precision computing system with precision-tuning, involving both hardware and software stack. In 2019, we have started the Minimal-Precision Computing project to propose a more broad concept of the minimal-precision computing system with precision-tuning, involving both hardware and software stack. Specifically, our system combines (1) a precision-tuning method based on Discrete Stochastic Arithmetic (DSA), (2) arbitrary-precision arithmetic libraries, (3) fast and accurate numerical libraries, and (4) Field-Programmable Gate Array (FPGA) with High-Level Synthesis (HLS). In this white paper, we aim to provide an overview of various technologies related to minimal- and mixed-precision, to outline the future direction of the project, as well as to discuss current challenges together with our project members and guest speakers at the LSPANC 2020 workshop; https://www.r-ccs.riken.jp/labs/lpnctrt/lspanc2020jan/

    Temperature Dependence of dV/dt Impact on the SiC-MOSFET

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    Silylative Kinetic Resolution of Racemic 1‑Indanol Derivatives Catalyzed by Chiral Guanidine

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    Efficient kinetic resolution of racemic 1-indanol derivatives was achieved using triphenylchlorosilane by asymmetric silylation in the presence of chiral guanidine catalysts. The chiral guanidine catalyst (<i>R,R</i>)-<i>N</i>-(1-(β-naphthyl)­ethyl)­benzoguanidine was found to be highly efficient as only 0.5 mol % catalyst loading was sufficient to catalyze the reaction of various substrates with appropriate conversion and high <i>s</i>-values (up to 89). This catalyst system was successfully applied to the gram-scale silylative kinetic resolution of racemic 1-indanol with high selectivity
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