Design-for-debug: A vital aspect in education

Paper presented at 2007 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '07, Honolulu, HI.We often assume that debugging is a skill that comes with common sense. However, we have observed that many students do not have an inherent aptitude for debugging. Hands-on projects teaching the engineering design process can become troublesome for some students who cannot complete their projects and consequently fail their courses. In this paper, we advocate the importance of teaching debugging skills throughout digital design courses, especially during the introductory courses. We present teaching techniques in developing the skills for debugging for both introductory and advanced digital design courses. These techniques include emphasis on incremental design stages, test stimuli and observation techniques, and debugging using critical (divergent and convergent) thinking

Jacobi load flow accelerator using FPGA

Paper presented at the 37th Annual North American Power Symposium, Ames, IA.Full-AC load flow is a crucial task in power system analysis. Solving full-AC load flow utilizes iterative numerical methods such as Jacobi, Gauss-Seidel or Newton- Raphson. Newton-Raphson is currently the preferred solver used in industrial applications such as Power World and PSS/E due to it faster convergence than either Jacobi or Gauss-Seidel. In this paper, we reexamine the Jacobi method for use in a fully pipelined hardware implementation using a Field Programmable Gate Array (FPGA) as an alternative to Newton-Raphson. Using benchmark data from representative power systems, we compare the operation counts of Newton-Raphson software to the proposed Jacobi FPGA hardware. Our studies show that Jacobi method implemented in an FPGA for a sufficiently large power system has the potential to be a state of the art full-AC load flow engine

Optimal reconfigurable HW/SW co-design of load flow and optimal power flow computation

Paper presented at IEEE Power Engineering Society General Meeting, Montreal, Quebec, Canada.Load flow and Optimal Power Flow (OPF) constitute core computations used in energy market operation. We considered different design partitions of computational tasks for a desktop computer equipped with Field Programmable Gate Array (FPGA). Load flow and OPF require Lower-Upper triangular matrix decomposition (LU). The number of clock cycles required for data transfer and floating-point operations were used as performance measures in determining optimal hardware/software partitions for each problem. Optimal partition performance is achieved by assigning the Lower-Upper triangular decomposition (LU) and matrix multiplication operations to custom hardware cores. A comparison between the proposed partition and software implemented using a state-of-the-art sparse matrix package running on a 3.2 GHz Pentium 4 shows a six-fold speedup