A Prototype of a New Generation Readout ASIC in 65 nm CMOS for Pixel Detectors at HL-LHC

The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments. This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications. It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS. The prototype is composed of a matrix of 64×64 pixels with 50 μm × 50 μm cells featuring a compact design, low-noise and low-power performance. The pixel array integrates two different analogue front-end architectures working in parallel, one with asynchronous and one with synchronous hit discriminators. Common characteristics are a compact layout able to fit into half the pixel size, low-noise performance (ENC < 100 e− RMS for 50 fF input capacitance), below 5 μW/pixel power consumption, linear charge measurements up to 30 ke− input charge using Time-over-Threshold (ToT) encoding and leakage current compensation up to 50 nA per pixel. A novel region-based digital architecture has been designed in order to ensure > 99% efficiency for expected 3 GHz/cm2 hit rate, 1 MHz trigger rate and 12.5 μs trigger latency at HL-LHC. Pixels have been organized into regions of 4×4 cells and a common synthesized logic shared among all pixels provides a centralized memory for latency buffering, performs the trigger matching and handles the local configuration. The simulated particle inefficiency for this architecture is below 0.1% under nominal HL-LHC conditions. All global biases and voltages required by analogue front-ends are generated on-chip using 10-bit programmable DACs. Bias currents and voltages can be monitored by a 12-bit ADC. A bandgap voltage reference circuit provides a stable reference voltage for all these blocks. The readout of triggered data is based on replicated FIFOs placed at the chip periphery. Data are finally sent off-chip with 8b/10b encoding using a high-speed serializer. Triggerless and debug operating modes are also supported. Chip configuration and slow-control are performed through fully-duplex synchronous Serial Peripheral Interface (SPI) master/slave transactions. The I/O interface uses custom-designed JEDEC-compliant SLVS transmitters and receivers. All blocks and analogue front-ends have been silicon-proven during a previous prototyping phase and were demonstrated to be radiation tolerant up to 580 Mrad Total Ionizing Dose (TID) or beyond. The CHIPIX65 demonstrator was submitted for fabrication on July 2016. It was received back from the foundry on October 2016 and preliminary experimental characterizations started

A Prototype of a New Generation Readout ASIC in 65 nm CMOS for Pixel Detectors at HL-LHC

The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments. This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications. It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS. The prototype is composed of a matrix of 64×64 pixels with 50 μm × 50 μm cells featuring a compact design, low-noise and low-power performance. The pixel array integrates two different analogue front-end architectures working in parallel, one with asynchronous and one with synchronous hit discriminators. Common characteristics are a compact layout able to fit into half the pixel size, low-noise performance (ENC < 100 e− RMS for 50 fF input capacitance), below 5 μW/pixel power consumption, linear charge measurements up to 30 ke− input charge using Time-over-Threshold (ToT) encoding and leakage current compensation up to 50 nA per pixel. A novel region-based digital architecture has been designed in order to ensure > 99% efficiency for expected 3 GHz/cm2 hit rate, 1 MHz trigger rate and 12.5 μs trigger latency at HL-LHC. Pixels have been organized into regions of 4×4 cells and a common synthesized logic shared among all pixels provides a centralized memory for latency buffering, performs the trigger matching and handles the local configuration. The simulated particle inefficiency for this architecture is below 0.1% under nominal HL-LHC conditions. All global biases and voltages required by analogue front-ends are generated on-chip using 10-bit programmable DACs. Bias currents and voltages can be monitored by a 12-bit ADC. A bandgap voltage reference circuit provides a stable reference voltage for all these blocks. The readout of triggered data is based on replicated FIFOs placed at the chip periphery. Data are finally sent off-chip with 8b/10b encoding using a high-speed serializer. Triggerless and debug operating modes are also supported. Chip configuration and slow-control are performed through fully-duplex synchronous Serial Peripheral Interface (SPI) master/slave transactions. The I/O interface uses custom-designed JEDEC-compliant SLVS transmitters and receivers. All blocks and analogue front-ends have been silicon-proven during a previous prototyping phase and were demonstrated to be radiation tolerant up to 580 Mrad Total Ionizing Dose (TID) or beyond. The CHIPIX65 demonstrator was submitted for fabrication on July 2016. It was received back from the foundry on October 2016 and preliminary experimental characterizations started

Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC

A prototype of a new-generation readout ASIC targeting High-Luminosity (HL) LHC pixel detector upgrades has been designed and fabricated as part of the Italian INFN CHIPIX65 project using a commercial 65 nm CMOS technology. This demonstrator, hereinafter referred to as CHIPIX-FE0, is composed of a matrix of 64 7 64 pixels with 50 \ub5m 7 50 \ub5m pixel size embedding two different architectures of analog front-ends working in parallel. The final layout of the chip was submitted and accepted for fabrication on July 2016. Chips were received back from the foundry on October 2016 and successfully characterized before irradiation. Several irradiation campaigns with X-rays have been accomplished during 2017 at Padova INFN and CERN EP/ESE facilities under different uniformity and temperature conditions up to 630 Mrad Total Ionizing Dose (TID). These studies corfirmed negligible degradation of analog front-ends performance after irradiation. First sample chips have been also bump-bonded to 50 \ub5m 7 50 \ub5m and single readout electrode 25 \ub5m 7 100 \ub5m 3D sensors provided by Trento FBK. This represented a major milestone for the entire CHIPIX65 project, offering to the pixel community the first example of a complete readout chip in 65 nm CMOS technology coupled to such a kind of silicon detectors. Extensive characterizations with laser and radioactive sources have started. This paper briefly summarizes most important pre- and post-irradiation results, along with preliminary results obtained from chips bump-bonded to 3D sensors. Selected components of the CHIPIX65 demonstrator have been finally integrated into the large-scale RD53A prototype submitted at the end of summer 2017 by the CERN RD53 international collaboration on 65 nm CMOS technology

Design of analog front-ends for the RD53 demonstrator chip

The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment

RD53 Collaboration and CHIPIX65 Project for the development of an innovative Pixel Front End Chip for HL-LHC

Pixel detectors at HL-LHC experiments will be exposed to unprecedented level of radiation and particle flux. This paper describes the program of development of an innovative pixel chip using a CMOS 65nm technology for the first time in HEP community, for experiments with extreme particle rates and radiation at future High Energy Physics colliders. The RD53 collaboration effort is described together with the CHIPIX65 INFN project

Phosphaditylserine liposomes as a possible candidate for the therapeutic management of Mycobacterium abscessus infection in CF patients

Introduction: we have previously reported that phosphatidylserine liposome (PS-L) were capable to induce a significant antimycobacterial response in mycobacterium tuberculosis (MTB)-infected and MTB/HIV-1-coinfected macrophages by simultaneously limiting inflammatory response and HIV replication. Here, we have assessed the therapeutic value of PS-L on human macrophages in vitro infected with M. abscessus (Mab), a non-tubercular mycobacterium which represents a relevant cause of morbidity and mortality in vulnerable patients such as those with cystic fibrosis (CF). Materials and methods: Differentiated THP-1 cells (dTHP-1), used as a model of human macrophages, and primary macrophages derived from CF patients, were in vitro infected with Mab and then stimulated or not PS-L. the therapeutic value of the treatment was assessed in terms of intracellular mycobacterial viability, by CFU assay, and NF-kB activation (calculated as the ratio between total NF-κB and phosphorylated NF-κB) by NFκB p65 (Total/Phospho) Human InstantOneTM ELISA Kit (Invitrogen) results: results show that in vitro stimulation with PS-L of dTHP-1 cells in vitro infected with mab significantly reduces intracellular mycobacterial viability and was associated with a significant drop in NF-κB activation. Importantly, such pro-mycobacteriocidal effect was also observed on macrophages from cystic fibrosis patients in vitro infected with Mab. discussion and conclusions: altogether, these results extend our previously reported results obtained on MTB-infected and MTB/HIV-coinfected cells, also against a relevant difficult-to-treat non tubercular mycobacterium, such as Mab, and support the therapeutic exploitation of PS-L as host-directed therapy to simultaneously limit potentially pathogenetic proinflammatory response and intracellular Mab viability in vulnerable patients, such as CF patients

Integrated front-end electronics for Silicon PhotoMultiplier readout in medical imaging applications

The 4D-MPET project aims to design a positron emission tomography detection module capable of working inside a magnetic resonant imaging system. The proposed detector will feature a three-dimensional architecture based on two tiles of silicon photomultipliers coupled to a single LYSO scintillator on both its faces. Silicon photomultipliers are magnetic-field compatible photo-detectors with a very small size enabling novel detector geometries that allowthe measurement of the depth of interaction. Furthermore they can be fabricated using standard silicon technology, have a large gain in the order of 106 and are very fast thus allowing evaluating the time of flight. Based on custom integrated circuits, the readout electronics include an innovative current mode front-end coupled to a novel time to digital converter. The former, implemented in AMS 0.35 μm SiGe-BiCMOS technology, features a very low input impedance (17 Ω) current buffer and a large bandwidth (1 GHz), which lead to a time resolution of ∼100 ps FWHM. The time to digital converter exploits the combination of a submicron technology (UMC 65 nm LLLVT) together with a systolic topology so as to work at a high frequency of 2.5 GHz. This yields to a nominal time resolution of 29 ps (σ) whereas the photon energy is evaluated with a bin size of 400 ps by using a time over threshold technique. Finally, the depth of interaction measurement is performed by an external FPGA with a simulated spatial resolution of 1.3 mm FWHM along the z coordinat

Combined host- and pathogen-directed therapy for the control of mycobacterium abscessus infection

Mycobacterium abscessus is the etiological agent of severe pulmonary infections in vulnerable patients, such as those with cystic fibrosis (CF), where it represents a relevant cause of morbidity and mortality. Treatment of pulmonary infections caused by M. abscessus remains extremely difficult, as this species is resistant to most classes of antibiotics, including macrolides, aminoglycosides, rifamycins, tetracyclines, and β-lactams. Here, we show that apoptotic body like liposomes loaded with phosphatidylinositol 5-phosphate (ABL/PI5P) enhance the antimycobacterial response, both in macrophages from healthy donors exposed to pharmacological inhibition of cystic fibrosis transmembrane conductance regulator (CFTR) and in macrophages from CF patients, by enhancing phagosome acidification and reactive oxygen species (ROS) production. The treatment with liposomes of wild-type as well as CF mice, intratracheally infected with M. abscessus, resulted in about a 2-log reduction of pulmonary mycobacterial burden and a significant reduction of macrophages and neutrophils in bronchoalveolar lavage fluid (BALF). Finally, the combination treatment with ABL/PI5P and amikacin, to specifically target intracellular and extracellular bacilli, resulted in a further significant reduction of both pulmonary mycobacterial burden and inflammatory response in comparison with the single treatments. These results offer the conceptual basis for a novel therapeutic regimen based on antibiotic and bioactive liposomes, used as a combined host- and pathogen-directed therapeutic strategy, aimed at the control of M. abscessus infection, and of related immunopathogenic responses, for which therapeutic options are still limited. IMPORTANCE Mycobacterium abscessus is an opportunistic pathogen intrinsically resistant to many antibiotics, frequently linked to chronic pulmonary infections, and representing a relevant cause of morbidity and mortality, especially in immunocompromised patients, such as those affected by cystic fibrosis. M. abscessus-caused pulmonary infection treatment is extremely difficult due to its high toxicity and long-lasting regimen with life-impairing side effects and the scarce availability of new antibiotics approved for human use. In this context, there is an urgent need for the development of an alternative therapeutic strategy that aims at improving the current management of patients affected by chronic M. abscessus infections. Our data support the therapeutic value of a combined host- and pathogen-directed therapy as a promising approach, as an alternative to single treatments, to simultaneously target intracellular and extracellular pathogens and improve the clinical management of patients infected with multidrug-resistant pathogens such as M. abscessus

TDC-based readout electronics for real-time acquisition of high resolution PET bio-images

Positron emission tomography (PET) is a clinical and research tool for in vivo metabolic imaging. The demand for better image quality entails continuous research to improve PET instrumentation. In clinical applications, PET image quality benefits from the time of flight (TOF) feature. Indeed, by measuring the photons arrival time on the detectors with a resolution less than 100 ps, the annihilation point can be estimated with centimeter resolution. This leads to better noise level, contrast and clarity of detail in the images either using analytical or iterative reconstruction algorithms. This work discusses a silicon photomultiplier (SiPM)-based magnetic-field compatible TOF-PET module with depth of interaction (DOI) correction. The detector features a 3D architecture with two tiles of SiPMs coupled to a single LYSO scintillator on both its faces. The real-time front-end electronics is based on a current-mode ASIC where a low input impedance, fast current buffer allows achieving the required time resolution. A pipelined time to digital converter (TDC) measures and digitizes the arrival time and the energy of the events with a timestamp of 100 ps and 400 ps, respectively. An FPGA clusters the data and evaluates the DOI, with a simulated z resolution of the PET image of 1.4 mm FWH

First measurements of a prototype of a new generation pixel readout ASIC in 65 nm CMOS for extreme rate HEP detectors at HL-LHC

A first prototype of a readout ASIC in CMOS 65 nm for a pixel detector at High Luminosity LHC is described. The pixel cell area is 50x50 mu m(2) and the matrix consists of 64x64 pixels. The chip was designed to guarantee high efficiency at extreme data rates for very low signals and with low power consumption. Two different analogue front-end designs, one synchronous and one asynchronous, were implemented, both occupying an area of 35x35 mu m(2). ENC value is below 100 e(-) for an input capacitance of 50 IF and in-time threshold below 1000 e(-) Leakage current compensation up to 50 nA with power consumption below 5 mu W. A ToT technique is used to perform charge digitization with 5-bit precision using either a 40 MHz clock or a local Fast Oscillator up to 800 MHz. Internal 10-hit DAC's are used for biasing, while monitoring is provided by a 12-bit ADC. A novel digital architecture has been developed to ensure above 99.5% hit efficiency at pixel hit rates up to 3 GHz/cm(2), trigger rates up to 1 MHz and trigger latency of 12.5 mu s. The total power consumption per pixel is below 5 mu W. Analogue dead-time is below 1%. Data are sent via a serializer connected to a CMOS-to-SLVS transmitter working at 320 MHz. All IP-blocks and front-ends used are silicon-proven and tested after exposure to ionizing radiation levels of 500-800 Mrad. The chip was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 and was submitted in July 2016 for production. Early test results for both front-ends regarding minimum threshold, auto-zeroing and low-noise performance are high encouraging and will be presented in this paper