3 research outputs found

    Development of silicon planar P-I-N photodiode

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    Optical receivers are used to detect optical power and to extract the information that is being transmitted. The incident optical power is detected by a photo detector, usually a PIN or avalanche photodiode (APD). A PIN or APD is an amplitude modulation envelope photo detector, insensitive to phase or small changes in wavelength. It generates an electrical output that reproduces the envelope of the received optical signal (Li, 2000). The most widely deployed photodiode for all lightwave applications is the PIN photodiode where its performance and characteristics are well understood and documented (Campbell, 1995)

    Investigation on optical interconnect(OI) link performance using external modulator

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    This paper investigates and analyzes an Optical Interconnect (OI) link using external (indirect) modulation technique. A Continuous Wave (CW) light source with a Mach Zehnder (MZ) modulator is used in the transmitter part and a Si-based waveguide is used as a transmission path. Indium Gallium Arsenide (InGaAs) and Germanium (Ge) materials were applied to observe the performance of Avalanche Photodiode (APD) and P-I-N Photodiode (PIN). In order to evaluate the performance of OI link using external (indirect) modulation, the model of OI link was designed and simulated using OptiSPICE tools. Simulation results on the performance of MZ modulator, power degradation of OI link and receiver sensitivity are reported in this paper

    Numerical investigation of channel width variation in junctionless transistors performance

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    Double gate junctionless (DGJLT) transistor, as a pinch off device, was previously fabricated. In this letter, the impact of channel width variation on behaviour of the device is studied by means of 3D-TCAD simulation tool. In this matter, the transfer characteristics, energy band diagram (valence/conduction band) and normal electric field along the nanowire between the source and the drain are studied at pinch off state. By decreasing the nanowire width, the on current decreases. Threshold voltage also reduced by decreasing the wire width. The highest electric field occurs at off state and the normal component of the electric field is stronger for smaller channel width. At pinch off state, the energy band diagrams revealed that a potential barrier against the current flow was built in channel which the smallest width has higher potential barrier. The overall result agrees with the behaviour of the nanowire junctionless transistors
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