Optimization of production test of analog and RF circuits using statistical modeling techniques

International audienc

Optimisation du test de production de circuits analogiques et RF par des techniques de modélisation statistique

ISBN : 978-2-84813-171-9The share of test in the cost of design and manufacture of integrated circuits continues to grow, hence the need to optimize this step. In this thesis, new methods of test scheduling and reducing the number of tests are proposed. The solution is a sequence of tests for early identification of faulty circuits, which can also be used to eliminate redundant tests. These test methods are based on statistical modeling of the circuit under test. This model included several parametric and non-parametric models to adapt to all types of circuit. Once the model is validated, the suggested test methods generate a large sample containing defective circuits. These allow a better estimation of test metrics, particularly the defect level. Based on this error, a test scheduling is constructed by maximizing the detection of faulty circuits. With few tests, the Branch and Bound method is used to obtain the optimal order of tests. However, with circuits containing a large number of tests, heuristics such as decomposition method, genetic algorithms or floating search methods are used to approach the optimal solution.La part dû au test dans le coût de conception et de fabrication des circuits intégrés ne cesse de croître, d'où la nécessité d'optimiser cette étape devenue incontournable. Dans cette thèse, de nouvelles méthodes d'ordonnancement et de réduction du nombre de tests à effectuer sont proposées. La solution est un ordre des tests permettant de détecter au plus tôt les circuits défectueux, qui pourra aussi être utilisé pour éliminer les tests redondants. Ces méthodes de test sont basées sur la modélisation statistique du circuit sous test. Cette modélisation inclus plusieurs modèles paramétriques et non paramétrique permettant de s'adapté à tous les types de circuit. Une fois le modèle validé, les méthodes de test proposées génèrent un grand échantillon contenant des circuits défectueux. Ces derniers permettent une meilleure estimation des métriques de test, en particulier le taux de défauts. Sur la base de cette erreur, un ordonnancement des tests est construit en maximisant la détection des circuits défectueux au plus tôt. Avec peu de tests, la méthode de sélection et d'évaluation est utilisée pour obtenir l'ordre optimal des tests. Toutefois, avec des circuits contenant un grand nombre de tests, des heuristiques comme la méthode de décomposition, les algorithmes génétiques ou les méthodes de la recherche flottante sont utilisées pour approcher la solution optimale

Réduction de tests fonctionnels par modélisation statistique des circuits analogiques

National audienceThe constant increase in the integration level of microelectronics technologies makes possible to manufacture more complex devices, including parts or blocks of heterogeneous nature. However, because of the difficulties of access to the blocks of a system, the problems of test become increasingly important, generating extremely high costs. This work addresses this problem by using a statistical modelling of the performances of the analogue blocks for the optimization of the functional test. The method suggested is based on the evaluation of test metrics, in particular the defect level like criterion of elimination of the performances to be tested. This makes possible during the production test to classify the functional and failing circuits with an optimal number of measurements of test and a reduction of the total test time

Réduction de tests fonctionnels par modélisation statistique des circuits analogiques

National audienceThe constant increase in the integration level of microelectronics technologies makes possible to manufacture more complex devices, including parts or blocks of heterogeneous nature. However, because of the difficulties of access to the blocks of a system, the problems of test become increasingly important, generating extremely high costs. This work addresses this problem by using a statistical modelling of the performances of the analogue blocks for the optimization of the functional test. The method suggested is based on the evaluation of test metrics, in particular the defect level like criterion of elimination of the performances to be tested. This makes possible during the production test to classify the functional and failing circuits with an optimal number of measurements of test and a reduction of the total test time

Ordering of analog specification tests based on parametric defect level estimation

ISBN 978-1-4244-6649-8International audienceThis paper presents an approach for ordering analog specification (or functional) tests that is based on a statistical estimation of parametric defect level. A statistical model of n specification tests is obtained by applying a density estimation technique to a small sample of data (obtained from the initial phase of production testing or through Monte-Carlo simulation of the design). The statistical model is next sampled to generate a large population of synthetic devices from which specification tests can be ordered according to their impact on defect level by means of feature selection techniques. An optimal order can be obtained using the Branch and Bound method when n is relatively low. However, for larger values of n, heuristic methods such as genetic algorithms and floating search must be used which do not guarantee an optimal order. Since the value of n can reach several hundreds for advanced analog integrated devices, we have studied a heuristic algorithm that considers combinations of subsets of the overall test set. These subsets are easier to model and to order and a heuristic approach is used to form an overall order. This test ordering approach is evaluated for different artificial and experimental case-studies, including a fully differential operational amplifier. These case-studies are simple enough so that it is possible to compare the results obtained with the algorithm with an expected reference order

Analog/RF test ordering in the early stages of production testing

ISBN 978-1-4673-1073-4International audienceOrdering of analog/RF tests is important for the identification of redundant tests. Most methods for test ordering are based on a representative set of defective devices. However, at the beginning of production testing, there is little or no data on defective devices. Obtaining this data through defect and fault simulation is unrealistic for most advanced analog/RF devices. In this work, we will present a method for analog/RF test ordering that uses only data from a small set of functional circuits. A statistical model of the device under test is constructed from this data. This model is next used for sampling a large number of virtual circuits which will also include defective ones. These virtual defective circuits are then used for ordering analog/RF tests using feature selection techniques. Experimental results for an IBM RF front-end have demonstrated the validity of this technique for test grading and compaction

Minimization of functional tests by statistical modelling of analogue circuits

International audienceIn this paper, we address the problem of functional test compaction of analogue circuits by using a statistical model of the performances of the Circuit Under Test (CUT). The statistical model is obtained using data from a Monte Carlo simulation and uses a multi-normal law to estimate the joint probability density function (PDF) of the circuit performances at the design stage. The functional test compaction method is based on the minimization of the defect level, again at the design stage, that is calculated from the estimated PDF and the actual specifications of the circuit performances. The suitability of the actual reduced functional test set for production test is evaluated in terms of its capability of detecting catastrophic faults

Structural, microstructural and Mössbauer studies of nanocrystalline Fe100-x Alx powders elaborated by mechanical alloying

Nanocrystalline Fe100-xAlx powders (x= 25, 30, 34 and 40 at %) were prepared by the mechanical alloying process using a vario-planetary high-energy ball mill for a milling time of 35 h. The formation and physical properties of the alloys were investigated as a function of Al content by means of X-ray diffraction, scanning electron microscopy (SEM), energy dispersive X-ray and Mössbauer spectroscopy. For all Fe100-xAlx samples, the complete formation of bcc phase was observed after 35 h of milling. As Al content increases, the lattice parameter increases, whereas the grain size decreases from 106 to 12 nm. The powder particle morphology for different compositions was observed by SEM. The Mössbauer spectra were adjusted with a singlet line and a sextet containing two components. The singlet was attributed to the formation of paramagnetic A2 disordered structure rich with Al. About the sextet, the first component indicated the formation of Fe clusters/ Fe-rich phases; however, the second component is characteristic of disordered ferromagnetic phase

Functional test compaction by statistical modelling of analogue circuits

International audienceIn this paper, we address the problem of functional test compaction of analogue circuits by using a statistical model of the performances of the Circuit Under Test (CUT). The statistical model is obtained using data from a Monte-Carlo simulation and uses a multi-normal law to estimate the joint Probability Density Function (PDF) of the circuit performances at the design stage. The functional test compaction method is based on the minimization of the defect level, again at the design stage, that is calculated from the estimated PDF and the actual specifications of the circuit performances. The suitability of the actual reduced functional test set for production test must next be evaluated in terms of its capability of detecting catastrophic and parametric faults

Minimization of functional tests by statistical modelling of analogue circuits

ISBN : 1-4244-1278-1International audienceIn this paper, we address the problem of functional test compaction of analogue circuits by using a statistical model of the performances of the Circuit Under Test (CUT). The statistical model is obtained using data from a Monte Carlo simulation and uses a multi-normal law to estimate the joint probability density function (PDF) of the circuit performances at the design stage. The functional test compaction method is based on the minimization of the defect level, again at the design stage, that is calculated from the estimated PDF and the actual specifications of the circuit performances. The suitability of the actual reduced functional test set for production test is evaluated in terms of its capability of detecting catastrophic faults