High-Level Synthesis Techniques for Reducing the Activity of Functional Units

Decisions taken at the earliest steps of the design process may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled during high-level synthesis (high-level transformations, scheduling and binding). Several techniques pursuing low power are proposed and the potential benefits evaluated. The common idea behind these techniques is to reduce the activity of the functional units (e.g. adders, multipliers) by minimizing the changes of their input operands. Preliminary evaluations obtained from switch-level simulations show that significant improvements can be achieved. 1 Introduction Power consumption can be taken into account at different levels [5]: technological, topological, architectural and algorithmic level. High-level synthesis (HLS) comprises techniques at the architectural and algorithmic level. Traditionally, HLS has been applied to obtain small and fast designs. But little has been done ..

Scheduling and Resource Binding for Low Power

Decisions taken at the earliest steps of the design process may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled during the scheduling and resource-binding steps of high-level synthesis. Algorithms for these steps targeting at low-power data-paths and trading off, in some cases, speed and area for low power are presented. The algorithms focus on reducing the activity of the functional units (adders, multipliers) by minimizing the transitions of their input operands. The power consumption of the functional units accounts for a large fraction of the overall data-path power budget. 1 Introduction Current VLSI technology allows circuits with more and more functionality to be integrated in just one chip. Nowadays, portable applications are not only wrist clocks or calculators but multi-media terminals, mobile telephones and other real-time systems. These new applications are based on intensive ..

Optimizing CMOS Circuits for Low Power using Transistor Reordering

This paper addresses the optimization of a circuit for low power using transistor reordering. The optimization algorithm relies on a stochastic model of a static CMOS gate that includes the power of internal nodes of the gate. This power-consumption model depends on the switching activity and the equilibrium probabilities of the inputs of the gate. The model allows an exploration of the different configurations of a gate that are obtained by reordering its transistors. Thus, the best configuration of each gate is selected and the overall power consumption of the circuit is reduced. 1 Introduction The continuous increasing packing density and clock frequency of static CMOS circuits has pushed low power as one of the principal design parameters, specially in batterypowered portable systems, such as note-pad computers, personal digital assistants, multi-media terminals and mobile telephones. This paper addresses the optimization of a circuit for low power using transistor reordering fro..

Reducing Energy Consumption of Flip-Flops

Flip-flops are one of the most power-consuming components of digital circuits. Even when there is no activity at their inputs, the mere triggering of the clock produces a significant waste of energy. This paper presents some techniques to reduce power consumption by selectively deactivating the clock when flip-flops do not have to change their value. Several flip-flop structures are proposed and criteria are given to select among them to obtain the minimum energy consumption. These novel structures may impose some timing constraints on the pulse widths of the clock. These constraints are analyzed and their influence on the circuit's performance evaluated. In some applications where the next state of the flip-flop depends on the present value (such as accumulators), the use of selective activation might result in a simplification of the combinational network, resulting in additional energy savings. By combining these techniques with novel coding approaches for redundant representations,..

Universe Model 11.0 overview: Gaia Report to ESA (GAIA-C2-TN-LAOB-AR-004-11)

International audienc

Universe Model 11.0 overview

International audienc

Universe Model 13.0 overview: Gaia Report to ESA (GAIA-C2-TN-LAOB-AR-004-13)

International audienc

Universe Model 13.0 overview: Gaia Report to ESA (GAIA-C2-TN-LAOB-AR-004-13)

International audienc