Optimisation du procédé de réalisation pour l'intégration séquentielle 3D des transistors CMOS FDSOI

L activation à basse température est prometteuse pour l intégration 3D séquentielle où lebudget thermique du transistor supérieur est limité (<650 C) pour ne pas dégrader letransistor inférieur, mais aussi dans le cas d une intégration planaire afin d atteindre des EOTultra fines et de contrôler le travail de sortie de la grille sans recourir à une intégration de type gate-last . Dans ce travail, l activation par recroissance en phase solide (SPER) a étéétudiée afin de réduire le budget thermique de l activation des dopants.L activation à basse température présente plusieurs inconvénients. Les travauxprécédents montrent que les fuites de jonctions sont plus importantes dans ces dispositifs.Ensuite, des fortes désactivations de dopants ont été observées. Troisièmement, la faiblediffusion des dopants rend difficile la connexion des jonctions source et drain avec le canal.Dans ce travail, il est montré que dans un transistor FDSOI, l augmentation des fuites dejonctions et la désactivation du Bore peuvent être évités grâce à la présence de l oxyde enterré.De plus les conditions d implantation ont été optimisées et les transistors activés à650 C atteignent les performances des transistors de référence.Low temperature (LT) process is gaining interest in the frame of 3D sequentialintegration where limited thermal budget (<650 C) is needed for top FET to preserve bottomFET from any degradation and also in the standard planar integration for achieving ultra-thinEOT and work function control with high-k metal gate without gate-last integration scheme.In this work, LT Solid Phase Epitaxial Regrowth (SPER) has been investigated for reducingthe most critical thermal budget which is dopant activation.From previous works, LT activated devices face several challenges: First, higher junctionleakage limits their application to high performance devices. Secondly, strong deactivation ofthe metastable activated dopants was observed with post anneals. Thirdly, the dopant weakdiffusion makes it difficult to connect the channel with S/D.In this work, it is shown that the use of FDSOI enables to overcome junction leakage andBoron deactivation issues thanks to the defect cutting off and sinking effect of buried oxide.As a consequence, dopant deactivation in FDSOI devices is no longer an issue. Finally,implants conditions of LT transistors have been optimized to reach similar performance thanits standard high temperature counterparts.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Caractérisation électrique de transistors sans jonctions avec simulation numérique

L'invention du premier transistor à Bell lab's, dans le groupe de W. Shockley, en 1947 a été suivie d'une ère de développement des circuits intégrés (IC). Depuis plusieurs dizaines d'années, la dimension critique des transistors métal/oxyde/semi-conducteurs (les transistors MOS), la longueur physique de la grille, a diminué à un rythme régulier. Cette évolution, motivée par des raisons économiques, a été anticipée par G. Moore, et est de ce fait connue sous le nom de "loi de Moore". La dimension de grille a d'ores et déjà été réduite de plus de 2 ordres de grandeur et, dans son édition2012, l'association ITRS prédit qu'elle décroîtra encore, de 22nm en 2011 à environ 6nm en 2026 [1].Toutefois, cette réduction des dimensions fait apparaître un certain nombre d'effets secondaires qui altèrent le fonctionnement idéal des transistors MOS [2].In this dissertation, the performance of junction less transistors (JLTs) as possible candidates for the continuation of Moore s law was investigated experimentally based on an in-depth study of their electrical characteristics. Current-voltage I-V and capacitance-voltage C-V were analyzed in a wide rangeof temperatures (from 80 K to 350 K) in correlation with device operation mechanism. Lowfrequencynoise was also studied and compared to that of inversion-mode transistors. This study requirednew parameter extraction methods to be defined for JLTs. Their validity was confirmed by 2-dimensional (2D) simulation results. They will be detailed in this dissertation.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Electrical characterization and modeling of low dimensional nanostructure FET

At the beginning of this thesis, basic and advanced device fabrication process which I haveexperienced during study such as top-down and bottom-up approach for the nanoscale devicefabrication technique have been described. Especially, lithography technology has beenfocused because it is base of the modern device fabrication. For the advanced device structure,etching technique has been investigated in detail.The characterization of FET has been introduced. For the practical consideration in theadvanced FET, several parameter extraction techniques have been introduced such as Yfunction,split C-V etc.FinFET is one of promising alternatives against conventional planar devices. Problem ofFinFET is surface roughness. During the fabrication, the etching process induces surfaceroughness on the sidewall surfaces. Surface roughness of channel decreases the effectivemobility by surface roughness scattering. With the low temperature measurement andmobility analysis, drain current through sidewall and top surface was separated. From theseparated currents, effective mobilities were extracted in each temperature conditions. Astemperature lowering, mobility behaviors from the transport on each surface have differenttemperature dependence. Especially, in n-type FinFET, the sidewall mobility has strongerdegradation in high gate electric field compare to top surface. Quantification of surfaceroughness was also compared between sidewall and top surface. Low temperaturemeasurement is nondestructive characterization method. Therefore this study can be a propersurface roughness measurement technique for the performance optimization of FinFET.As another quasi-1 D nanowire structure device, 3D stacked SiGe nanowire has beenintroduced. Important of strain engineering has been known for the effective mobility booster.The limitation of dopant diffusion by strain has been shown. Without strain, SiGe nanowireFET showed huge short channel effect. Subthreshold current was bigger than strained SiGechannel. Temperature dependent mobility behavior in short channel unstrained device wascompletely different from the other cases. Impurity scattering was dominant in short channelunstrained SiGe nanowire FET. Thus, it could be concluded that the strain engineering is notnecessary only for the mobility booster but also short channel effect immunity.Junctionless FET is very recently developed device compare to the others. Like as JFET,junctionless FET has volume conduction. Thus, it is less affected by interface states.Junctionless FET also has good short channel effect immunity because off-state ofjunctionless FET is dominated pinch-off of channel depletion. For this, junctionless FETshould have thin body thickness. Therefore, multi gate nanowire structure is proper to makejunctionless FET.Because of the surface area to volume ratio, quasi-1D nanowire structure is good for thesensor application. Nanowire structure has been investigated as a sensor. Using numericalsimulation, generation-recombination noise property was considered in nanowire sensor.Even though the surface area to volume ration is enhanced in the nanowire channel, devicehas sensing limitation by noise. The generation-recombination noise depended on the channelgeometry. As a design tool of nanowire sensor, noise simulation should be carried out toescape from the noise limitation in advance.The basic principles of device simulation have been discussed. Finite difference method andMonte Carlo simulation technique have been introduced for the comprehension of devicesimulation. Practical device simulation data have been shown for examples such as FinFET,strongly disordered 1D channel, OLED and E-paper.At the beginning of this thesis, basic and advanced device fabrication process which I haveexperienced during study such as top-down and bottom-up approach for the nanoscale devicefabrication technique have been described. Especially, lithography technology has beenfocused because it is base of the modern device fabrication. For the advanced device structure,etching technique has been investigated in detail.The characterization of FET has been introduced. For the practical consideration in theadvanced FET, several parameter extraction techniques have been introduced such as Yfunction,split C-V etc.FinFET is one of promising alternatives against conventional planar devices. Problem ofFinFET is surface roughness. During the fabrication, the etching process induces surfaceroughness on the sidewall surfaces. Surface roughness of channel decreases the effectivemobility by surface roughness scattering. With the low temperature measurement andmobility analysis, drain current through sidewall and top surface was separated. From theseparated currents, effective mobilities were extracted in each temperature conditions. Astemperature lowering, mobility behaviors from the transport on each surface have differenttemperature dependence. Especially, in n-type FinFET, the sidewall mobility has strongerdegradation in high gate electric field compare to top surface. Quantification of surfaceroughness was also compared between sidewall and top surface. Low temperaturemeasurement is nondestructive characterization method. Therefore this study can be a propersurface roughness measurement technique for the performance optimization of FinFET.As another quasi-1 D nanowire structure device, 3D stacked SiGe nanowire has beenintroduced. Important of strain engineering has been known for the effective mobility booster.The limitation of dopant diffusion by strain has been shown. Without strain, SiGe nanowireFET showed huge short channel effect. Subthreshold current was bigger than strained SiGechannel. Temperature dependent mobility behavior in short channel unstrained device wascompletely different from the other cases. Impurity scattering was dominant in short channelunstrained SiGe nanowire FET. Thus, it could be concluded that the strain engineering is notnecessary only for the mobility booster but also short channel effect immunity.Junctionless FET is very recently developed device compare to the others. Like as JFET,junctionless FET has volume conduction. Thus, it is less affected by interface states.Junctionless FET also has good short channel effect immunity because off-state ofjunctionless FET is dominated pinch-off of channel depletion. For this, junctionless FETshould have thin body thickness. Therefore, multi gate nanowire structure is proper to makejunctionless FET.Because of the surface area to volume ratio, quasi-1D nanowire structure is good for thesensor application. Nanowire structure has been investigated as a sensor. Using numericalsimulation, generation-recombination noise property was considered in nanowire sensor.Even though the surface area to volume ration is enhanced in the nanowire channel, devicehas sensing limitation by noise. The generation-recombination noise depended on the channelgeometry. As a design tool of nanowire sensor, noise simulation should be carried out toescape from the noise limitation in advance.The basic principles of device simulation have been discussed. Finite difference method andMonte Carlo simulation technique have been introduced for the comprehension of devicesimulation. Practical device simulation data have been shown for examples such as FinFET,strongly disordered 1D channel, OLED and E-paper.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Booth for Nanonets2Sense project presentation

session poster : EFECS 2017 exhibition (#29)International audienc

Nanonets2Sense – Nanonet-based integrated sensors for health and well-being: Integration concept and project overview

International audienc

Nanonet-based field effect devices for label-free sensing

International audienc

Nanonets2Sense - integrated sensors for health and well-being: project overview

International audienc

Etude de la mobilité dans des transistors intégrant un oxyde de forte permittivité et une grille métallique

Afin de satisfaire aux exigences imposées par la Roadmap ITRS, l industrie microélectronique doit envisager un certain nombre de révolutions dans ses procédés de fabrication des composants. En effet, la seule miniaturisation des dimensions du transistor à effet de champ Métal-Oxyde-Semiconducteur (MOSFET) ne suffit plus à améliorer les performances des dispositifs. Parmi les solutions envisagées, l une des plus prometteuses consiste à remplacer l isolant de grille historique en oxyde de silicium (SiO2) et la grille en polysilicium par un couple constitué d une grille métallique et d un matériau isolant possédant une plus forte permittivité diélectrique. Ce travail présente ainsi les effets du couple grille TiN/dioxyde d hafnium HfO2 sur les performances électriques d un MOSFET en étudiant la mobilité des porteurs libres en régime d inversion.In order to follow the more and more constraining ITRS Roadmap specifications, the microelectronic industry has to deal with many modifications in its way to process electronic components. Indeed, only shrinking the dimensions of the Metal-Oxide-Semiconductor Field effect Transistor (MOSFET) has become insufficient to reach the expected performance and new approaches have to be imagined. One of the most promising solutions is to replace the "historical" SiO2 gate oxide and the polysilicon gate by a metal gate deposited on a high-k material. This work reports on the influence of the TiN/HfO2 stack on the electrical performances of a MOSFET by studying a characteristic parameter of electrical transport in the conduction layer : carrier mobility in the inversion channel. A theoretical study of the different scattering processes that limit mobility in these new architectures was first realized. In a second step, innovating experimental techniques were developed to extract the mobility (magnetoresistance measurements, pulsed split C-V...) and precisely characterize the set of devices. Using these two complementary approaches, we were able to determine the dominant scattering processes which are responsible for carrier mobility degradation when a TiN metal gate and an HfO2 high-k layer are used.GRENOBLE1-BU Sciences (384212103) / SudocSudocFranceF

Etude théorique et optimisation des performances de linéarité des transistors bipolaires SiGe et SiGeC en vue de l'amélioration des compromis gain/bruit/linéarité/consommation des fonctions intégrées radiofréquences des récepteurs multi-modes de 3ème génération

L'objectif de cette thèse est de comprendre le comportement non linéaire du TBH utilisé pour un LNA à une fréquence de 2GHz. Une première méthode basée sur l'implémentation et la simulation d'un TBH équivalent non linéaire a été mise en oeuvre. Cette démarche nous a permis d'identifier les sources de non linéarité, sans pour autant nous permettre de comprendre l'implication des éléments du TBH. C'est pourquoi nous avons appliqué la théorie de Volterra. Les courants de distorsion sont alors exprimés sous forme littérale en fonction des paramètres du TBH ainsi que des impédances de source et de charge. Cette approche a été validée sur un LNA émetteur commun et sur un LNA cascode en technologie BiCMOS 0.25 m SiGeC. La contribution des non linéarités de la capacité base collecteur vis à vis de la distorsion globale des montages a été mise en évidence.GRENOBLE1-BU Sciences (384212103) / SudocSudocFranceF

Contribution à l étude des non-linéarités du troisième ordre des mélangeurs BiCMOS

Les normes actuelles de télécommunications sont très strictes en termes de linéarité. Malgré son rôle critique, 1e mélangeur a fait l'objet de peu d'études théoriques sur ce point. L'objet de cette thèse est de fournir une analyse théorique du mélangeur (constitué ici d'une cellule de Gilbert réalisée en technologie BiCMOS SiGe) permettant d identifier, entre autre, l'origine des distorsions d'ordre 3 (IMD3), qui peuvent amener des signaux parasites au voisinage de la porteuse. Nous avons mis en oeuvre et validé deux méthodes basées sur le formalisme des série de Volterra qui permettent, grâce à une approche analytique, d'identifier les paramètres du transistor impliqué dans la distorsion en fonction des conditions (fréquence, niveau des entrées) et de la technologie utilisée. Cette étude souligne en outre le rôle de la commutation dans la dégradation de la linéarité et fournit les bases pour un étude complète du phénomène.Present telecommunication standards are very stringent in tenns of linearity. Despite its critical role, mixer linearity has been the subject of few theoretical studies in literature. The goal of this thesis is to provide a theoretical analysis of the mixer (here a Gilbert cell, realized using a BiCMOS SiGe technology), making it possible to identify the origin of distortions, with special focus on the 3rd order intennodulation distortion (IMD3) that bring parasitic signaIs close to carrier frequency. We implemented and validated two methods, based on the Volterra series. Thanks to the analytical approach used here, it becomes possible to identify the transistor parameters that an anbe origin of distortions, as a function of the context (frequency, signallevels...) and of technology. ln addition, this study specifies the role of switching in linearity degradation and provides the bases for a complete study of the mixer.GRENOBLE1-BU Sciences (384212103) / SudocSudocFranceF