PixFEL: development of an X-ray diffraction imager for future FEL applications

A readout chip for diffraction imaging applications at new generation X-ray FELs (Free Electron Lasers) has been designed in a 65 nm CMOS technology. It consists of a 32 × 32 matrix, with square pixels and a pixel pitch of 110 µm. Each cell includes a low-noise charge sensitive amplifier (CSA) with dynamic signal compression, covering an input dynamic range from 1 to 104 photons and featuring single photon resolution at small signals at energies from 1 to 10 keV. The CSA output is processed by a time-variant shaper performing gated integration and correlated double sampling. Each pixel includes also a small area, low power 10-bit time-interleaved Successive Approximation Register (SAR) ADC for in-pixel digitization of the amplitude measurement. The channel can be operated at rates up to 4.5 MHz, to be compliant with the rates foreseen for future X-ray FEL machines. The ASIC has been designed in order to be bump bonded to a slim/active edge pixel sensor, in order to build the first demonstrator for the PixFEL (advanced X-ray PIXel cameras at FELs) imager

The WaveDAQ integrated Trigger and Data Acquisition System for the MEG II experiment

The WaveDAQ is a newly-designed digitization Trigger and Data AcQuisition system (TDAQ) allowing Multi-gigasample waveform recording on a large amount of channels (up to 16384) by using the DRS4 analog switched capacitor array as downconverting ASIC. A high bandwidth, programmable input stage has been coupled with a bias generator to allow SiPM operation without need of any other external apparatus. The trigger generation is tightly coupled within the system to limit the required depth of the analog memory, allowing faster digitization speeds. This system has been designed for the MEG experiment upgrade but also proved to be highly scalable and already found other applications.Comment: This manuscript is for conference record of the 21st IEEE Real Time conference onl

GINGER

In this paper, we outline the scientific objectives, the experimental layout, and the collaborations envisaged for the GINGER (Gyroscopes IN GEneral Relativity) project. The GINGER project brings together different scientific disciplines aiming at building an array of Ring Laser Gyroscopes (RLGs), exploiting the Sagnac effect, to measure continuously, with sensitivity better than picorad/ s, large bandwidth (ca. 1 kHz), and high dynamic range, the absolute angular rotation rate of the Earth. In the paper, we address the feasibility of the apparatus with respect to the ambitious specifications above, as well as prove how such an apparatus, which will be able to detect strong Earthquakes, very weak geodetic signals, as well as general relativity effects like Lense-Thirring and De Sitter, will help scientific advancements in Theoretical Physics, Geophysics, and Geodesy, among other scientific fields.Comment: 21 pages, 9 figure

Initial experience with the CDF SVT trigger

The Collider Detector at Fermilab (CDF) Silicon Vertex Tracker (SVT) is a device that works inside the CDF Level 2 trigger to find and fit tracks in real time using the central silicon vertex detector information. SVT starts from tracks found by the Level 1 central chamber fast trigger and adds the silicon information to compute transverse track parameters with offline quality in about . The CDF SVT is fully installed and functional and has been exercised with real data during the spring and summer 2001. It is a complex digital device of more than 100 VME boards that performs a dramatic data reduction (only about one event in a thousand is accepted by the trigger). Diagnosing rare failures poses a special challenge and SVT internal data flow is monitored by dedicated hardware and software. This paper briefly covers the SVT architecture and design and reports on the SVT building/commissioning experience (hardware and software) and on the first results from the initial running

Quadruple Well CMOS MAPS With Time-Invariant Processor Exposed to Ionizing Radiation and Neutrons

Monolithic active pixel sensors featuring a time-invariant front-end channel have been fabricated in a quadruple well CMOS process in the frame of an R&D project aiming at developing low material budget, radiation hard detectors for tracking applications. MAPS prototypes have been exposed to integrated fluences up to 10^14 1 MeV neutron equivalent / cm^2 to test the device tolerance to bulk damage also for different values of the epitaxial layer resistivity. Moreover, samples of the same device have been irradiated with y-rays from a 60Co source, reaching a final dose exceeding 10 Mrad, to study ionizing radiation effects. This work discusses the test results, obtained through different measurement techniques, and the mechanisms underlying performance degradation in irradiated quadruple well CMOS MAPS

CMOS MAPS in a homogeneous 3D process for charged particle tracking

This work presents the characterization of deep n-well (DNW) CMOS monolithic active pixel sensors (MAPS) fabricated in a 130 nm homogeneous, vertically integrated technology. An evaluation of the 3D MAPS device performance, designed for application of the experiments at the future high luminosity colliders, is provided through the characterization of the prototypes, including tests with infrared (IR) laser, 55Fe and 90Sr sources. The radiation hardness study of the technology will also be presented together with its impact on 3D DNW MAPS performance

Modeling Charge Loss in CMOS MAPS Exposed to Non-Ionizing Radiation

A model, approximating minority carrier diffusion with a discrete random walk and accounting for radiation induced reduction of minority carrier lifetime, is proposed to predict the effects of neutron irradiation on the charge collection properties of monolithic active pixel sensors (MAPS) in CMOS technology. The model has been implemented in a Monte Carlo code to simulate MAPS operation in minimum ionizing particle detection systems. For the purpose of validating it, the results from the characterization of monolithic sensors irradiated up to an integrated fluence of 10^14 1 MeV neutron equivalent / cm^2 have been compared with the outcomes of the Monte Carlo simulations. The monolithic sensors taken into consideration for the model validation are based on two different CMOS processes, one featuring a triple well option, the other one featuring a quadruple well structure and a standard (10 ohm cm) or high (1 kohm cm) resistivity epitaxial layer. Simulation results are shown to be in good agreement with experimental data. The consistency between the model and the measurement results seems to confirm that radiation induced increase in the recombination rate is the main source of charge collection degradation in neutron-irradiated MAPS

Front-end performance and charge collection properties of heavily irradiated DNW MAPS

Deep N-well (DNW) CMOS monolithic active pixel sensors (MAPS) fabricated in a 130 nm technology have been exposed to γ-rays up to an integrated dose of about 10 Mrad and subjected to a 100 °C/168 h annealing cycle. Device tolerance to total ionizing dose has been evaluated by monitoring the change in charge sensitivity, noise and charge collection properties after each step of the irradiation and annealing campaign. Damage mechanisms and their relation to front-end architecture and sensor features are thoroughly discussed by comparing the response to ionizing radiation of different test structures and based on radiation induced degradation models in single MOS transistors

Effects of Substrate Thinning on the Properties of Quadruple Well CMOS MAPS

The chip prototype Apsel4well, including monolithic active pixel sensor (MAPS) test structures, has been designed for vertexing applications requiring a fast and low material silicon vertex tracker. The chip is fabricated in a 180 nm CMOS process called INMAPS, featuring a quadruple well and a high resistivity epitaxial layer option. The main advantage with this approach lies in the chance of increasing the in-pixel intelligence as compared to standard three transistor MAPS schemes. Moreover, the presence of the quadruple well and of the high resistivity epitaxial layer leads to better charge collection performance and radiation resistance. Different samples of the Apsel4well chip have been thinned down to about 25 mu m and 50 mu m. This minimization of the material can further improve the tracker performance virtually with no charge signal loss. At the beginning, this paper focuses on the results from charge collection TCAD simulations of the Apsel4well pixel structure performed at different thicknesses and substrate bias voltages. Later on, results from measurements relevant to the thinned chips both in terms of analog front-end channel performance and charge collection properties will be shown and compared to those from non-thinned chips