Photonic Neural Networks and Optics-informed Deep Learning Fundamentals

The recent explosive compute growth, mainly fueled by the boost of AI and DNNs, is currently instigating the demand for a novel computing paradigm that can overcome the insurmountable barriers imposed by conventional electronic computing architectures. PNNs implemented on silicon integration platforms stand out as a promising candidate to endow NN hardware, offering the potential for energy efficient and ultra-fast computations through the utilization of the unique primitives of photonics i.e. energy efficiency, THz bandwidth and low-latency. Thus far, several demonstrations have revealed the huge potential of PNNs in performing both linear and non-linear NN operations at unparalleled speed and energy consumption metrics. Transforming this potential into a tangible reality for DL applications requires, however, a deep understanding of the basic PNN principles, requirements and challenges across all constituent architectural, technological and training aspects. In this tutorial, we, initially, review the principles of DNNs along with their fundamental building blocks, analyzing also the key mathematical operations needed for their computation in a photonic hardware. Then, we investigate, through an intuitive mathematical analysis, the interdependence of bit precision and energy efficiency in analog photonic circuitry, discussing the opportunities and challenges of PNNs. Followingly, a performance overview of PNN architectures, weight technologies and activation functions is presented, summarizing their impact in speed, scalability and power consumption. Finally, we provide an holistic overview of the optics-informed NN training framework that incorporates the physical properties of photonic building blocks into the training process in order to improve the NN classification accuracy and effectively elevate neuromorphic photonic hardware into high-performance DL computational settings

A 160Gb/s (4x40) WDM O-band Tx subassembly using a 4-ch array of silicon rings co-packaged with a SiGe BiCMOS IC driver

We present a 400 (8×50) Gb/s-capable RM-based Si-photonic WDM O-band TxRx with 1.17nm channel spacing for high-speed optical interconnects and demonstrate successful 50Gb/s-NRZ TxRx operation achieving a ~4.5dB Tx extinction ratio under 2.15Vpp drive

Temperature and wavelength drift tolerant WDM transmission and routing in on-chip silicon photonic interconnects

We demonstrate a temperature and wavelength shift resilient silicon transmission and routing interconnect system suitable for multi-socket interconnects, utilizing a dual-strategy CLIPP feedback circuitry that safeguards the operating point of the constituent photonic building blocks along the entire on-chip transmission-multiplexing-routing chain. The control circuit leverages a novel control power-independent and calibration-free locking strategy that exploits the 2nd derivative of ring resonator modulators (RMs) transfer function to lock them close to the point of minimum transmission penalty. The system performance was evaluated on an integrated Silicon Photonics 2-socket demonstrator, enforcing control over a chain of RM-MUX-AWGR resonant structures and stressed against thermal and wavelength shift perturbations. The thermal and wavelength stress tests ranged from 27 degrees C to 36 degrees C and 1309.90 nm to 1310.85 nm and revealed average eye diagrams Q-factor values of 5.8 and 5.9 respectively, validating the system robustness to unstable environments and fabrication variations. (C) 2022 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreemen

Co-Package Technology Platform for Low-Power and Low-Cost Data Centers

We report recent advances in photonic–electronic integration developed in the European research project L3MATRIX. The aim of the project was to demonstrate the basic building blocks of a co-packaged optical system. Two-dimensional silicon photonics arrays with 64 modulators were fabricated. Novel modulation schemes based on slow light modulation were developed to assist in achieving an efficient performance of the module. Integration of DFB laser sources within each cell in the matrix was demonstrated as well using wafer bonding between the InP and SOI wafers. Improved semiconductor quantum dot MBE growth, characterization and gain stack designs were developed. Packaging of these 2D photonic arrays in a chiplet configuration was demonstrated using a vertical integration approach in which the optical interconnect matrix was flip-chip assembled on top of a CMOS mimic chip with 2D vertical fiber coupling. The optical chiplet was further assembled on a substrate to facilitate integration with the multi-chip module of the co-packaged system with a switch surrounded by several such optical chiplets. We summarize the features of the L3MATRIX co-package technology platform and its holistic toolbox of technologies to address the next generation of computing challenges

Dithering-based real-time control of cascaded silicon photonic devices by means of non-invasive detectors

Real-time control of multiple cascaded devices is a key requirement for the development of complex silicon photonic circuits performing new sophisticated optical functionalities. This article describes how the dithering technique can be leveraged in combination with non-invasive light probes to independently control the working point of many photonic components. The standard technique is extended by introducing the concept of orthogonal dithering signals to simultaneously discriminate the effect of different actuators, while the idea of frequency re-use is discussed to limit the complexity of control systems in cascaded architectures. After a careful analysis of the problem, the article presents an automated feedback strategy to tune and lock photonic devices in the maxima/minima of their transfer functions with given response speed and sensitivity. The trade-offs of this approach are discussed in detail to provide guidelines for the design of the feedback loop. Experimental demonstrations on a mesh of Mach-Zehnder interferometers and on cascaded ring resonators are discussed to validate the proposed control architecture in different scenarios and applications

End-to-end optical packet switching with burst-mode reception at 25 Gb/s through a 1024-port 25.6 Tb/s capacity Hipoλaos Optical Packet Switch

We demonstrate end-to-end 25Gb/s true optical packet switching featuring burst-mode reception with <;50ns locking time through a 1024-port 25.6Tb/s capacity Hipoλaos Optical Packet Switch architecture. Error-free performance at 10 -9 was obtained for all validated port-combinations