Hybrid III–V/Silicon Nanowires

International audienceSemiconducting nanowires are emerging as a route to combine heavily mismatched materials. The nanowire dimensions facilitate the defect-free integration of the two most powerful semiconductor classes, group IVs and group III-Vs. These combinations may enhance the performance of existing device concepts, and also create new applications. In this chapter we review the recent progress in heteroepitaxial growth of III-V andIVmaterials. We highlight the advantage of using the small nanowire dimensions to facilitate accommodation of the lattice strain at the surface of the structures. Another advantage of the nanowire system is that anti phase boundaries are not formed, as there is only one nucleation site per wire. In this chapter, we will discuss three different heteroepitaxial III-V/Si morphologies, III-V nanowires on group IV substrates, and axial and radial heterojunctions. Advanced analysis techniques are used tocharacterise the quality of the heterointerfaces. Finally, we address potential applications of III-V/Si nanowires

Single photon emission and detection at the nanoscale utilizing semiconductor nanowires

We report recent progress toward on-chip single photon emission and detection in the near infrared utilizing semiconductor nanowires. Our single photon emitter is based on a single InAsP quantum dot embedded in a p-n junction defined along the growth axis of an InP nanowire. Under forward bias, light is emitted from the single quantum dot by electrical injection of electrons and holes. The optical quality of the quantum dot emission is shown to improve when surrounding the dot material by a small intrinsic section of InP. Finally, we report large multiplication factors in excess of 1000 from a single Si nanowire avalanche photodiode comprised of p-doped, intrinsic, and n-doped sections. The large multiplication factor obtained from a single Si nanowire opens up the possibility to detect a single photon at the nanoscale.Comment: 11 pages, 7 figure

Residual strain and piezoelectric effects in passivated GaAs/AlGaAs core-shell nanowires

International audienceWe observe a systematic red shift of the band-edge of passivated GaAs/Al0.35Ga0.65As core-shell nanowires with increasing shell thickness up to 100 nm. The shift is detected both in emission and absorption experiments, reaching values up to 14 meV for the thickest shell nanowires. Part of this red shift is accounted for by the small tensile strain imposed to the GaAs core by the AlGaAs shell, in line with theoretical calculations. An additional contribution to this red shift arises from axial piezoelectric fields which develop inside the nanowire core due to Al fluctuations in the shell

First Principles Assessment of CdTe as a Tunnel Barrier at the α\mathbf{\alpha}-Sn/InSb Interface

Majorana zero modes, with prospective applications in topological quantum computing, are expected to arise in superconductor/semiconductor interfaces, such as $\beta$-Sn and InSb. However, proximity to the superconductor may also adversely affect the semiconductor's local properties. A tunnel barrier inserted at the interface could resolve this issue. We assess the wide band gap semiconductor, CdTe, as a candidate material to mediate the coupling at the lattice-matched interface between $\alpha$-Sn and InSb. To this end, we use density functional theory (DFT) with Hubbard U corrections, whose values are machine-learned via Bayesian optimization (BO) [npj Computational Materials 6, 180 (2020)]. The results of DFT+U(BO) are validated against angle resolved photoemission spectroscopy (ARPES) experiments for $\alpha$-Sn and CdTe. For CdTe, the z-unfolding method [Advanced Quantum Technologies, 5, 2100033 (2022)] is used to resolve the contributions of different $k_z$ values to the ARPES. We then study the band offsets and the penetration depth of metal-induced gap states (MIGS) in bilayer interfaces of InSb/$\alpha$-Sn, InSb/CdTe, and CdTe/$\alpha$-Sn, as well as in tri-layer interfaces of InSb/CdTe/$\alpha$-Sn with increasing thickness of CdTe. We find that 16 atomic layers (3.5 nm) of CdTe can serve as a tunnel barrier, effectively shielding the InSb from MIGS from the $\alpha$-Sn. This may guide the choice of dimensions of the CdTe barrier to mediate the coupling in semiconductor-superconductor devices in future Majorana zero modes experiments

Avalanche amplification of a single exciton in a semiconductor nanowire

Interfacing single photons and electrons is a crucial ingredient for sharing quantum information between remote solid-state qubits. Semiconductor nanowires offer the unique possibility to combine optical quantum dots with avalanche photodiodes, thus enabling the conversion of an incoming single photon into a macroscopic current for efficient electrical detection. Currently, millions of excitation events are required to perform electrical read-out of an exciton qubit state. Here we demonstrate multiplication of carriers from only a single exciton generated in a quantum dot after tunneling into a nanowire avalanche photodiode. Due to the large amplification of both electrons and holes (> 10^4), we reduce by four orders of magnitude the number of excitation events required to electrically detect a single exciton generated in a quantum dot. This work represents a significant step towards single-shot electrical read-out and offers a new functionality for on-chip quantum information circuits

Generic nano-imprint process for fabrication of nanowire arrays

A generic process has been developed to grow nearly defect free arrays of (heterostructured) InP and GaP nanowires. Soft nanoimprint lithography has been used to pattern gold particle arrays on full 2 inch substrates. After lift-off organic residues remain on the surface, which induce the growth of additional undesired nanowires. We show that cleaning of the samples before growth with piranha solution in combination with a thermal anneal at 550 C for InP and 700 C for GaP results in uniform nanowire arrays with 1% variation in nanowire length, and without undesired extra nanowires. Our chemical cleaning procedure is applicable to other lithographic techniques such as e-beam lithography, and therefore represents a generic process.Comment: 12 pages, 4 figures, 2 table

From InSb Nanowires to Nanocubes: Looking for the Sweet Spot

High aspect ratios are highly desired to fully exploit the one-dimensional properties of indium antimonide nanowires. Here we systematically investigate the growth mechanisms and find parameters leading to long and thin nanowires. Variation of the V/III ratio and the nanowire density are found to have the same influence on the “local” growth conditions and can control the InSb shape from thin nanowires to nanocubes. We propose that the V/III ratio controls the droplet composition and the radial growth rate and these parameters determine the nanowire shape. A sweet spot is found for nanowire interdistances around 500 nm leading to aspect ratios up to 35. High electron mobilities up to 3.5 × 10^4 cm^2 V^(–1) s^(–1) enable the realization of complex spintronic and topological devices

Croissance et caractérisation électrique de nanocristaux d\u27InAs sur SiO2 pour des applications mémoires non volatiles sur silicium

Depuis la première proposition de 1995 de remplacer la grille flottante en polysilicium des mémoires non volatiles (MNV) par des nanocristaux de Si (nc-Si), la recherche est très active dans ce domaine. L\u27objectif de cette étude a consisté à fabriquer une MNV à nanocristaux d\u27InAs (nc-InAs) : en effet, utiliser l\u27InAs permettrait d\u27une part d\u27améliorer les caractéristiques des MNV grâce à son affinité électronique élevée, et d\u27autre part, d \u27évaluer les possibilités de stockage multibit dans un nanocristal unique. Tout d\u27abord, il s\u27est agit de faire croître les nc-InAs par épitaxie par jet moléculaire sur un oxyde tunnel SiO2 sur substrat Si. Les nc-InAs sont monocristallins et hémisphériques. Leur hauteur (2-12nm) dépend de la quantité de matière déposée et leur densité peut atteindre 7x10exp11cm-2. nous avons ensuite fabriqué des structures MOS à nc-InAs. Les temps d\u27écriture et effacement peuvent atteindre 1 micros à 12 V et 14 V respectivement. Finalement, nous avons démontré que l\u27utilisation des nc-In-As permet d\u27augmenter le temps de rétention de 2 décades par rapport aux nc-Si pour une structure de dimensions identique