Temperature and voltage measurement for field test using an Aging-Tolerant monitor

Measuring temperature and voltage (T&V) in a current VLSI is very important in guaranteeing its reliability, because a large variation of temperature or voltage in field will reduce a delay margin and makes the chip behavior unreliable. This paper proposes a novel method of T&V measurement, which can be used for variety of applications, such as field test, online test, or hot-spot monitoring. The method counts frequencies of more than one ring oscillator (RO), which composes an aging-tolerant monitor. Then, the T&V are derived from the frequencies using a multiple regression analysis. To improve the accuracy of measurement, three techniques of an optimal selection of RO types, their calibration, and hierarchical calculation are newly introduced. In order to make sure the proposed method, circuit simulation in 180-, 90-, and 45-nm CMOS technologies is performed. In the 180-nm CMOS technology, the temperature accuracy is within 0.99 °C, and the voltage accuracy is within 4.17 mV. Furthermore, some experimental results using fabricated test chips with 180-nm CMOS technology confirm its feasibility

Temperature and Voltage Estimation Using Ring-Oscillator-Based Monitor for Field Test

Field test is performed in diverse environments, in which temperature varies across a wide range. As temperature affects a circuit delay greatly, accurate temperature monitors are required. They should be placed at various locations on a chip including hot spots. This paper proposes a flexible ring-oscillator-based monitor that accurately measures voltage as well as temperature at the same time. The measurement accuracy was confirmed by circuit simulation for 180 nm, 90 nm and 45 nm technologies. An experiment using test chips with 180 nm technology shows its feasibility.2014 IEEE 23rd Asian Test Symposium (ATS), 16-19 Nov. 2014, Hangzhou, Chin

Reduction of NBTI-Induced Degradation on Ring Oscillators in FPGA

Ring Oscillators are used for variety of purposes to enhance reliability on LSIs or FPGAs. This paper introduces an aging-tolerant design structure of ring oscillators that are used in FPGAs. The structure is able to reduce NBTI-induced degradation in a ring oscillator\u27s frequency by setting PMOS transistors of look-up tables in an off-state when the oscillator is not working. The evaluation of a variety of ring oscillators using Altera Cyclone IV device (60nm technology) shows that the proposed structure is capable of controlling degradation level as well as reducing more than 37% performance degradation compared to the conventional oscillators.The 20th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2014), Nov 19-21, 2014, Singapor

卵巣明細胞癌に対するプリチデプシンの前臨床活性

Background/Aim: To evaluate the antitumor effects of Plitidepsin against clear cell carcinoma (CCC) of the ovary. Materials and Methods: The expression of eEF1A2 in ovarian cancer was assessed by immunohistochemistry. Using ovarian CCC cell lines, the antitumor effect of Plitidepsin was assessed both in vitro and in vivo. By over-expressing or knocking down the eEF1A2 expression, we investigated the role of eEF1A2 in the sensitivity of CCC cells to Plitidepsin. Results: Immunoreactivity to eEF1A2 was observed in 76.2% of CCC, which was significantly higher than other histological subtypes of ovarian cancer. Plitidepsin exhibited significant antitumor activity toward chemonaive and chemoresistant CCC cells both in vitro and in vivo. Ectopic expression of eEF1A2 in CCC cells resulted in increased sensitivity to Plitidepsin. In contrast, eEF1A2 knockdown decreased sensitivity of CCC cells to plitidepsin. Conclusion: Plitidepsin, a novel anti-cancer agent that targets eEF1A2, may be a promising agent for treating ovarian CCC.Clear cell carcinoma (CCC) of the ovary is known to be less sensitive to platinum-based frontline chemotherapy, and advanced-stage CCC is known to be associated with a worse prognosis than the more common histological subtype of serous adenocarcinoma (SAC). The lack of an effective chemotherapy for recurrent CCC is another important clinical problem (1). Therefore, novel strategies for both first-line treatment for advanced-stage CCC and salvage treatment for recurrent disease are needed. Plitidepsin (Aplidin®) is a novel anti-cancer agent currently investigated in late phases of clinical development. In 2018, the Australian regulatory agency approved Plitidepsin in combination with dexamethasone for the treatment of multiple myeloma. Plitidepsin was originally isolated from the Mediterranean tunicate Aplidium albicans in 1988: currently it is chemically synthesized by Pharma Mar (Madrid, Spain) (2). According to previous preclinical studies, Plitidepsin is active against a wide range of malignancies: hematological malignancies such as multiple myeloma, lymphoma, and leukemia, and solid tumors including non-small-cell lung carcinoma, pacncreas, breast, melanoma, sarcoma, gastric, and bladder cancer (3). Importantly, most reports demonstrated in vitro activity of Plitidepsin in a low nanomolar range. Accumulating evidence have suggested that Plitidepsin induces cell cycle arrest and apoptosis in a dose-dependent manner by inducing oxidative stress, decreasing intracellular levels of glutathione, upregulating the JNK and p38 MAPK pathways. In addition to cytotoxic and cytostatic activities, Plitidepsin is known to inhibit tumor-angiogenesis through the inhibition of vascular endothelial growth factor (VEGF) secretion from cancer cells. In ovarian cancer, Plitidepsin exhibited anti-proliferative activity in vitro, and significantly inhibited the growth of a xenograft in athymic mice. However, since most ovarian cancer cell lines used in the previous preclinical studies of Plitidepsin were derived from ovarian SAC, the therapeutic potential of Plitidepsin against ovarian CCC is unknown. The translation factor eEF1A2 is a tissue-specific variant of the eukaryotic Elongation Factor 1. The expression of eEF1A2 is normally confined to muscles and neurons (4). However, eEF1A2 is frequently over-expressed in various human malignancies and has oncogenic properties. Anand et al. (5) were the first to show that eEF1A2, while not normally expressed in ovary, is expressed in 30% of ovarian tumors. When examined according to histological subtypes, eEF1A2 was highly expressed in clear cell ovarian tumors compared to other histological subtypes of ovarian cancer (6). A recent study demonstrated that approximately 75% of ovarian CCC showed over-expression of eEF1A2 at the protein level (7). Although detailed mechanisms of action have not been completely investigated, Plitidepsin has been suggested to exert its antitumor activity by directly interacting with eEF1A2. Thus, plitidepsin might be a potential drug candidate for the treatment of CCC showing over-expression of eEF1A2. In the current study, after investigating the expression rate of eEF1A2 in ovarian cancer specimens, we evaluated the in vitro and in vivo therapeutic efficacy of Plitidepsin as a single agent against both chemonaive and chemorefractory ovarian CCC cells

On-chip delay measurement for in-field test of FPGAs

Avoidance of delay-related failures due to aging phenomena is an important issue of current VLSI systems. Delay measurement in field is effective for detection of aging-induced delay increase. This paper proposes a delay measurement method using BIST (Built-In Self-Test) in an FPGA. The proposed method consists of variable test timing generation using an embedded PLL, BIST-based delay measurement, and correction of the measured delay with reflecting temperature variance in field. In on-chip delay measurement of the proposed method, the fastest operating speed is checked by repeating delay test with several test timings. Because circuit delay is influenced by temperature during measurement, the measured delay is then corrected according to the temperature during testing. Based on test log including the corrected delay, delay degradation and aging detection can be grasped. In evaluation experiments of the propose method implemented on an Intel Cyclone IV FPGA device (60nm technology), variable test timing generation realized 96 ps timing step resolution (that is below 1% of the system clock), correction process for measured delay could reduce influence of temperature variation. Furthermore, its feasibility of the proposed method for aging detection is discussed in this paper.24th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2019), December 1-3, 2019, Kyoto, Japa

A selection method of ring oscillators for an on-chip digital temperature and voltage sensor

An on-chip digital sensor using three types of ring oscillators (ROs: Ring Oscillators) has been proposed to measure temperature and voltage of a VLSI. Each RO has inherent frequency characteristics with respect to temperature and voltage, which differ from those of the other two ROs. Measurement accuracy of the sensor depends on the combination of the ROs. This paper proposes a RO-selection method for the sensor with high accuracy. The proposed method takes particular note of temperature or voltage sensitivity as well as linearity of the RO characteristics. Evaluation experiments with SPICE simulation in 65 nm CMOS technology show that the temperature and voltage accuracies of the sensor are 2.744°C and 3.825mV, respectively, and the selected combination was a nearly optimal from a menu of many different ROs.The 3rd International Test Conference in Asia (ITC-Asia 2019), September 3-5, 2019Tokyo Denki University, Tokyo, Japa

Path Delay Measurement with Correction for Temperature And Voltage Variations

Path delay measurement in field is useful for not only detection of delay-related faults but also prediction of aging-induced delay faults. In order to utilize the delay measurement results for fault detection and fault prediction, the measured delay must be corrected because the circuit delay is varied in field due to environment such as temperature or voltage variations. This paper proposes a method of BIST-based path delay measurement in which the influence of environmental variations is eliminated. An on-chip sensor measures temperature and voltage during delay measurement. Using information from the temperature and voltage sensor and pre-computed temperature and voltage sensitivities of the circuit delay, the measured delay value is corrected to a delay value that would be obtained under a fixed temperature and voltage. Evaluation for a test chip with 65nm CMOS technology implementing the proposed method shows that errors of measured delays brought by environmental variations could be reduced from 2419 to 211 ps in the range of 30 to 80 °C and 1.05 to 1.35 V. This paper also discusses application and feasibility for degradation detection of the proposed method.International Test Conference in Asia (ITC-Asia 2020), September 23-25, 2020, Taipei City, Taiwan（現地およびオンラインで開催