Variation of Sidewall Passivation on Sub-um Selectively Grown Ge-on-Si Devices Towards Single Photon Avalanche Detectors

Developing single photon avalanche diodes (SPADs) at short-wave infrared (SWIR) wavelengths beyond 1000 nm has attracted interest lately. Numerous quantum technology applications such as light detection and ranging (LIDAR), imaging through obscurants and quantum communications require sensitivity in this region. In quantum communications, operation at the telecoms wavelengths of 1310 nm and 1550 nm is essential. Ge-on-Si SPADs offer potential for lower afterpulsing and higher single photon detection efficiencies in the SWIR in comparison with InGaAs/InP SPADs, at a lower cost due to Si foundry compatibility. In this study, Ge-on-Si devices are fabricated on silicon-on-insulator (SOI) substrates, with a separate absorption, charge and multiplication layer (SACM) geometry and a lateral Si multiplication region. This Si foundry compatible process will allow for future integration with Si waveguides and optical fibres. The Ge is selectively grown inside sub-μm wide SiO2 trenches, reducing the threading dislocation in comparison with bulk Ge; a typical process for integrated Ge detectors. Here we deliberately exposed Ge sidewalls with an etch-back technique, to allow a passivation comparison not normally carried out in selectively grown devices planarised by chemical-mechanical polishing. Reduced dark currents are demonstrated using thermal GeO2 passivation in comparison to plasma-enhanced chemical-vapourdeposition SiO2. The improved passivation performance of GeO2 is verified by activation energy extraction and density of interface trap (Dit) calculations obtained from temperature-dependent capacitance-voltage (CV) and conductance-voltage (GV) measurements. This highlights the benefit of optimal surface passivation on sub-μm wide selectively grown Ge-on-SOI photodetector devices, potentially critical for waveguide integrated SPADs

Current leakage mechanisms related to threading dislocations in Ge-rich SiGe heterostructures grown on Si(001)

This work investigates the role of threading dislocation densities (TDD) in the low density regime on the vertical transport in Si0.06Ge0.94 heterostructures integrated on Si(001). The use of unintentionally doped Si0.06Ge0.94 layers enables the study of the impact of grown-in threading dislocations (TD) without interaction with processing-induced defects originating, e.g., from dopant implantation. The studied heterolayers, while equal in composition, the degree of strain relaxation, and the thickness feature three different values for the TDD as 3 × 106, 9 × 106, and 2 × 107 cm−2. Current–voltage measurements reveal that leakage currents do not scale linearly with TDD. The temperature dependence of the leakage currents suggests a strong contribution of field-enhanced carrier generation to the current transport with the trap-assisted tunneling via TD-induced defect states identified as the dominant transport mechanism at room temperature. At lower temperatures and at high electric fields, direct band-to-band tunneling without direct interactions with defect levels becomes the dominating type of transport. Leakage currents related to emission from mid-gap traps by the Shockley–Read–Hall (SRH) generation are observed at higher temperatures (>100 °C). Here, we see a reduced contribution coming from SRH in our material, featuring the minimal TDD (3 × 106 cm−2), which we attribute to a reduction in point defect clusters trapped in the TD strain fields

Scope of sesame (Sesamum indicum L.) in Pakistan

In IDL-704

Si Nanowires and their Transistor Properties

Si nanowires have a multitude of potential applications including transistors, memories, photovoltaics, thermoelectrics and qubits. For 10 nm scaled transistors, planar gate geometries due not provide sufficient electrostatic control of the channel and so nanowires have been suggested as a solution. Here we demonstrate a gate wrap-around metal-oxide semiconductor field effect transistor (MOSFET) using a Si nanowire as the channel. The devices were fabricated using top down electron-beam lithography, low damage dry etch, thermal oxidation and Al based metal. Transmission electron microscope images indicate a nanowire width of 8.0 ± 0.5 nm with a gate oxide of 16 nm. 150 nm gate length devices demonstrate excellent electrostatic control of the channel with Ion to Ioff ratios above 108, minimum subthreshold slopes of 66 mV/dec and Ion up to 35 μA/nanowire (4.4 mA/μm gate width) at VD = Vg = 1.5 V

Si Nanowires and their Transistor Properties

Si nanowires have a multitude of potential applications including transistors, memories, photovoltaics, thermoelectrics and qubits. For 10 nm scaled transistors, planar gate geometries due not provide sufficient electrostatic control of the channel and so nanowires have been suggested as a solution. Here we demonstrate a gate wrap-around metal-oxide semiconductor field effect transistor (MOSFET) using a Si nanowire as the channel. The devices were fabricated using top down electron-beam lithography, low damage dry etch, thermal oxidation and Al based metal. Transmission electron microscope images indicate a nanowire width of 8.0 ± 0.5 nm with a gate oxide of 16 nm. 150 nm gate length devices demonstrate excellent electrostatic control of the channel with Ion to Ioff ratios above 108, minimum subthreshold slopes of 66 mV/dec and Ion up to 35 μA/nanowire (4.4 mA/μm gate width) at VD = Vg = 1.5 V

Electron Transport in Top-down Fabricated Silicon Nanowires Using Relaxed and Scalable Nanofabrication

Silicon nanowire have shown promising potential in wide range of next generation CMOS electronics [1], opto-electronics, sensing applications [1] and quantum information processing. The strong confinement required to make quantum processes robust to temperature fluctuations and other scattering processes across large numbers of devices as required for many quantum computing proposals in silicon normally requires the aggressive scaling of devices to sub-10 nm dimensions which requires high quality lithography and well controlled etch processes [2-4]. Here we demonstrate a new approach to achieving high performance silicon nanowires using more relaxed lithography of 20 to 50 nm combined with multiple oxidation and etches to reduce the diameter of the silicon nanowires to less than half the written lithography linewidths. Temperature dependent electron transport measurements are used to determine the electronic scattering processes which limit the transport and a comparison is made to more conventional 8.0 ± 0.5 nm nanowires fabricated without the multiple oxidations and etches. Limitations of the technique along with the potential for scaling the technique for the mass fabrication of millions of devices will be discussed. 1. C. Busche, et. al., Nature 515, 545 (2014). 2. M.M. Mirza, et al., Nano Letters 14, 6056 (2014). 3. M.M. Mirza, et al., Scientific Reports, 7, 3004 (2017). 4. M.M. Mirza, et al., JVST-B, 30, 06FF02 (2012)

Thermal and Plasma Enhanced Atomic Layer Deposition of Al2O3 and HfO2 Films Investigated by Using in situ Auger Electron Spectroscopy

No abstract available

Thermal and Plasma Enhanced Atomic Layer Deposition of Al2O3 and HfO2 Films Investigated by Using in situ Auger Electron Spectroscopy

No abstract available

Many-Body Effects in 1D Degenerately-Doped Silicon Nanowire Devices

Nanowire transistors are being investigated to solve short-channel effects in future CMOS technology nodes [1][2] but such devices are also a potential scalable platform for quantum information processing devices. Here we demonstrate degenerately-doped silicon nanowires with 8.0 ± 0.5 nm diameter using a wrap-around gate junction-less transistor based on silicon-on-insulator (SOI) structure [1], fabricated using top-down approach involves electron-beam lithography [2], low damage dry etch [3] and thermal oxidation. As the nanowire diameter is scaled below the Fermi wavelength, the channel switches from metallic to insulating behaviour demonstrating 1D electron transport characteristics with excellent electrostatic control of the channel. In this regime, near ideal sub-threshold (SS) slopes of 66 mV/dec at room temperature, Ion/Ioff ratios above 108 and Ion up to 35 μA/nanowire (4.4 mA/μm gate width) at VD=Vg=1.5 V are observed. Universal conductance scaling as a function of voltage and temperature comparable to previous reports of Luttinger liquid transport and Coulomb gap behaviour at low temperatures indicate that many body effects including electron-electron interactions are significant in describing the electron transport. Our results indicates many body effects such as electron-electron interactions are essential in determining the electron transport in such ultra-scaled nanowires. Routes to multiple gate devices for coupled quantum dots will be described. 1. M.M. Mirza, et al., Scientific Reports, 7, 3004 (2017). 2. C. Busche, et. al., Nature 515, 545 (2014). 3. M.M. Mirza, et al., JVST-B, 30, 06FF02 (2012)