Silicon nanowire have shown promising potential in wide range of next generation CMOS electronics [1], opto-electronics, sensing applications [1] and quantum information processing. The strong confinement required to make quantum processes robust to temperature fluctuations and other scattering processes across large numbers of devices as required for many quantum computing proposals in silicon normally requires the aggressive scaling of devices to sub-10 nm dimensions which requires high quality lithography and well controlled etch processes [2-4]. Here we demonstrate a new approach to achieving high performance silicon nanowires using more relaxed lithography of 20 to 50 nm combined with multiple oxidation and etches to reduce the diameter of the silicon nanowires to less than half the written lithography linewidths. Temperature dependent electron transport measurements are used to determine the electronic scattering processes which limit the transport and a comparison is made to more conventional 8.0 ± 0.5 nm nanowires fabricated without the multiple oxidations and etches. Limitations of the technique along with the potential for scaling the technique for the mass fabrication of millions of devices will be discussed.
1. C. Busche, et. al., Nature 515, 545 (2014).
2. M.M. Mirza, et al., Nano Letters 14, 6056 (2014).
3. M.M. Mirza, et al., Scientific Reports, 7, 3004 (2017).
4. M.M. Mirza, et al., JVST-B, 30, 06FF02 (2012)
