Invited; Latch-up issue between high-voltage circuit domain and low-voltage circuit domain in TFT LCD driver IC fabricated with BCD process

To drive the TFT LCD display panel, the driver ICs must be equipped with the low-voltage (LV) circuits and highvoltage (HV) together in a single chip to achieve the necessary circuit functions. The LV circuits are used to receive and decode the input signals from computers, as well as the HV circuits are used to send the output signals to the TFT LCD panel for display. With mixed-voltage circuits integrated in a single chip, the parasitic lateral latch-up path wouldl be formed between the neighboring HV-to-LV circuit blocks. When such a parasitic latch-up path was triggered on by external overshooting/undershooting transient noises, it would cause serious burned-out failure located between the HV-to-LV circuit blocks in the chip. Please click Download on the upper right corner to see the full abstract

Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits

A novel electrostatic discharge (ESD) implantation method is proposed to significantly improve machinemodel (MM) ESD robustness of NMOS device in stacked configuration (stacked NMOS). By using this ESD implantation method, the ESD current is discharged far away from the surface channel of NMOS, therefore the stacked NMOS in the mixed-voltage I/O interface can sustain a much higher ESD level, especially under the MM ESD stress. The MM ESD robustness of the stacked NMOS with a device dimension of W/L=300µm/0.5µm for each NMOS has been successfully improved from the original 358V to become 491V in a 0.25-µm CMOS process. This ESD implantation method with the n-type impurity is fully process-compatible to general sub-quarter-micron CMOS processes. 1

New layout scheme to improve ESD robustness

Abstract -Silicidation used in CMOS processes has been reported to result in substantial degradation on ESD robustness of CMOS devices. In this work, a new ballasting layout scheme for fully-silicided I/O buffer is proposed to enhance its ESD robustness. Experimental results from real IC products have confirmed that the new ballasting layout scheme can successfully increase HBM ESD robustness of fully-silicided I/O buffers from 1.5kV to 7kV without using the additional silicide-blocking mask

Transient-induced latchup in CMOS integrated circuits

"Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description

Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits

Abstract CDM ESD event has become the main ESD reliability concern to product integrated circuits in nanoscale CMOS technology. A novel CDM ESD protection design, by using self-biased current trigger (SBCT) and source pumping, has been proposed and successfully verified in 0.13-μm CMOS technology to achiev

Overview on Latch-Up Prevention in CMOS Integrated Circuits by Circuit Solutions

In CMOS chips, the wider layout rules were traditionally applied to overcome latch-up issues. However, the chip area with wider layout rules was often enlarged, and in turn the chip cost was also increased. To effectively improve latch-up immunity without enlarging the chip area, circuit methods were therefore invented. An overview on circuit methodology used to prevent latch-up issues in CMOS integrated circuits (ICs) is presented in this article. The circuit solutions, including reducing the I/O pad trigger current, sensing the trigger current to control the power supply, and restarting the power supply through an MOS switch to shut off the latch-up current, are overviewed