Radiation-induced Effects on DMA Data Transfer in Reconfigurable Devices

As the adoption of SRAM-based FPGAs and Reconfigurable SoCs for High-Performance Computing increased in the last years, the use of Direct Memory Access for data transfer becomes a key feature of many reconfigurable applications even in the space industry. For such kinds of applications, radiation-induced effects are a serious issue that mines the correctness and success of mission-critical tasks. In this paper, we evaluate the effects of proton-induced errors on a DMA-based application implemented on a Xilinx Zynq-7020 FPGA in order to quantify the robustness of this module in a typical hardware-accelerated configuration. The obtained results confirm the high criticality of the DMA module on programmable logic. Moreover, the Multiple Bits Upsets effect has been evaluated. The most recurring patterns have been reported in order to provide further tools to better characterize the behavior of these systems under future fault injection campaigns, as demonstrated in the experimental results

Validation of a tool for estimating the effects of Soft- Errors on modern SRAM-based FPGAs

Predicting soft errors on SRAM-based FPGAs without a wasteful time-consuming or a high-cost has always been a very difficult goal. Among the available methods, we proposed an updated version of analytical approach to predict Single Event Effects (SEEs) based on the analysis of the circuit the FPGA implements. In this paper, we provide an experimental validation of this approach, by comparing the results it provides with a fault injection campaign. We adopted our analytical method for computing the error-rate of a design implemented on SRAM-based FPGA. Furthermore, we compared the obtained soft-error figure with the one measured by fault injection. Experimental analysis demonstrated the analytical method closely match the effective soft-error rates becoming a viable solution for the soft-error estimation at early design phase

Superimposed In-circuit fault mitigation for dynamically reconfigurable FPGAs

Reassuring fault tolerance in computing systems is the most important problem for mission critical space com- ponents. With the rise in interest of commercial SRAM-based FPGAs, it is crucial to provide runtime reconfigurable recovery from a failure. In this paper we propose a superimposed virtual coarse-grained reconfigurable architecture, embedded an on- demand three level fault-mitigation technique tailored for FPGA overlays. The proposed method performs run-time recovery via Microscrubbing. This approach can achieve up to 3× faster run- time recovery with 10.2× less resources in FPGA devices, by providing integrated layers of fault mitigation

Smart behavioral netlist simulation for SEU protection verification

Schulz S, Beltrame G, Merodio-Codinachs D. Smart behavioral netlist simulation for SEU protection verification. Esa Sp. 2008:406-411.This paper presents a novel approach to verify the correct implementation of Triple Modular Redundancy (TMR) for the memory elements of a given netlist using formal analysis. The purpose is detecting any issues that might incur during the use of automatic tools for TMR insertion, optimization, place and route, etc. Our analysis does not require a testbench and can perform full, exhaustive coverage within less than an hour even for large designs. This is achieved by applying a divide et impera approach, splitting the circuit into smaller submodules without loss of generality, instead of applying formal verification to the whole netlist at once. The methodology has been applied to a production netlist of the LEON2-FT processor that reported errors during radiation testing, successfully showing its TMR implementation issues

A new EDA flow for the Mitigation of SEUs in Dynamic Reconfigurable FPGAs

This work presents a new EDA flow that aims to increase the design robustness versus transient errors when the dynamic reconfigurable computing paradigm is adopted. In brief, we propose a modification of the existing commercial toolchain flow to make transient error aware designs. Aiming at that scope, a new algorithm for the design mapping has been developed reducing Single Event Upsets on the routing interactions between reconfigurable placed modules. The performance evaluation of the EDA flow has been evaluated with neutron-based radiation test experiments and fault injection using a proper dynamic reconfiguration context. Results prove a reduction of the transient error sensitivity about 3 orders of magnitude without any area overhead and with a performance degradation of less than 10% on the average

Analysis of radiation-induced SEUs on dynamic reconfigurable systems

SRAM-Based FPGAs are widely employed in space and avionics computing. The unfriendly environment and FPGA radiation sensibility can have dramatic drawbacks on the application reliability. The partial self-reconfiguration ability gives an excellent aid to counteract single event upsets (SEUs) caused by excessive silicon ionization, and the consequent system misbehavior. Related to this feature, fault injection and fault emulation and configuration scrubbing, has been carried out over three versions of a reconfigurable Fast Fourier Transform (FFT) system: a single FFT, a single larger FFT and a FFT with TMR architecture. The analysis has been focused on multiple injected SEUs scenario, considering the availability problem in a real-time application and highlighting the circuit tolerance at the upset presence. This operation has the goal to emulate as much as possible a real radiation test avoiding all the handicaps that this procedure involves. The obtained results have shown the advantages of the configuration scrubbing performed with the aim to fix multiple upsets, achieving up to 13.6% of circuit hardening. The achieved conclusions are an interesting starting point for the study of fault mitigation techniques through the use of reconfiguration. The projects have been tested on a Z-7010 AP So

A Reliable Fault Classifier for Dependable Systems on SRAM-based FPGAs

This paper presents an algorithm for the discrimination of faults in FPGAs based on their recovery possibility; some faults can be recovered by reconfiguring the faulty part of the device, others have a destructive effect. After classification has been carried out, the suitable fault recovery strategy is applied, with the final aim of enabling the exploitation of FPGAs, in particular SRAM-based ones, for critical applications, such as the ones in the space environment. In this scenario, we investigate the reliable implementation of the fault classification algorithm, that can be so integrated in an overall reliable system

Validation of a tool for estimating the effects of Soft- Errors on modern SRAM-based FPGAs

Predicting soft errors on SRAM-based FPGAs without a wasteful time-consuming or a high-cost has always been a very difficult goal. Among the available methods, we proposed an updated version of analytical approach to predict Single Event Effects (SEEs) based on the analysis of the circuit the FPGA implements. In this paper, we provide an experimental validation of this approach, by comparing the results it provides with a fault injection campaign. We adopted our analytical method for computing the error-rate of a design implemented on SRAM-based FPGA. Furthermore, we compared the obtained soft-error figure with the one measured by fault injection. Experimental analysis demonstrated the analytical method closely match the effective soft-error rates becoming a viable solution for the soft-error estimation at early design phases

On the Design of Highly Reliable System-on-Chip using Dynamically Reconfigurable FPGAs

Radiation-induced Soft Errors are widely known since the advent of dynamic RAM chips. Reconfigurable FPGA devices based on SRAM configuration memories are extremely sensitive to these effects resulting in an unwelcome change of behavior in digital logic. Indeed, soft errors occur today as a result of radiation from space or even at sea level. Detection, protection and mitigation of soft errors beyond aerospace and defence applications have been widely debated over the last decades. In the present paper we provide a complete design flow illustrating the proper design rules ranging from the synthesis, mapping and physical place and route algorithm tailored to the implementation of high performance and reliable SoCs using dynamic-reconfiguration oriented SRAM-based FPGAs. Radiation experimental results obtained radiation test performed using proton particles demonstrated the goodness of our developed design flow resulting in an overall error cross-section reduction of more than 2 orders of magnitud