Millimeter-Wave Radio Frequency Switch Design for 5th Generation Wireless Networks and Advanced Electrostatic Discharge Design

The fifth generation of wireless network technology is known as 5G. After 1G, 2G, 3G, and 4G, 5G is the next step in the wireless development. Compared with 4G Long Term Evolution (LTE), higher amounts of data can be transmitted more efficiently with 5G. This translates into superior speed data for dense areas, network access everywhere and low latency/high mobility connection, which can provide support for future user cases such as internet of things (IoTs), automotive, real-time remote surgery or cloud gaming. From these user cases, we can define the requirements of 5G: higher data rate, lower latency and better coverage. To achieve these requirements, there are several practical things we can do and actually, all research groups and companies are moving towards those directions, like macro base-station, beamforming, massive multiple input multiple output (MIMO) and millimeter-wave (mm-wave) band communication. These technologies will rely on more complex multi-band, multi-frequency front end module (FEM). The number of both antenna and FEM will increase for 5G. So as a bridge from chip to outside antenna, the antenna switch modules (ASM) performance will be more and more critical. Their performance must satisfy not only the criteria of insertion loss and isolation, but also the needs of 5G applications, which include faster data speeds, higher power and enhanced reliability. In this dissertation, ESD protected 28GHz, 38GHz and 60GHz wide-band travelling wave switches are presented in Chapter 3, which achieves comparable performance with state-of-art design and is the first travelling wave switch on SOI with co-design ESD protection. To reach a higher data rate with available frequency bands, millimeter wave (mm-wave) switches (38GHz/60GHz) has been demonstrated with the consideration of reliability issue of electrostatic discharge (ESD) which will introduce severe parasitic effects under this frequency level and degrade the performance of RFICs. The insertion loss and isolation together with ESD protection capability have been compared which shows the importance of ESD-RFIC co-design. On the other hand, it is reported recently that conventional pad-based charged-device-model (CDM) ESD protection method may be theoretically wrong. Chapter 4 analyzes the failure of classic pad-based ESD protection methods in CDM ESD protection and discusses a disruptively new non-pad-based internally distributed CDM ESD protection concept, which is demonstrated in an oscillator IC designed and fabricated in a 45nm SOI CMOS process. Design of novel interposer and through-silicon-via (TSV) based internal-distributed CDM ESD protection mesh networks are also presented. For first-silicon success and time-to-market, successful simulation before silicon is critical, especially for high-cost advanced technologies. The same is true for ESD protection. Chapter 5 introduces a new mixed-mode TCAD ESD simulation flow using combined HBM-TLP stimuli, or CDM-VFTLP stimuli, to enable ESD protection design prediction and verification. It provides a thorough analysis of various TCAD ESD simulation scenarios using both real-world HBM and CDM ESD waveforms, and their corresponding TLP and VFTLP square waveforms, in both single-pulse and pulse train manners, as stimuli. However, for large size MOSFET RF switch (width > 1mm), they are usually used as ESD self-protection device, which means no external ESD device will be added. In Chapter 6, we discussed the implementation of a novel ESD shell model which enables the ESD self-protection simulation for RF switches for cell phone FEMs. As verified in hardware, >98% accuracy using simulation results can be achieved. Moreover, the ESD shell model can be easily placed in parallel to the FET base model in the schematic which is a simple and cost-effective solution to enable predictive ESD simulations of FEM switch devices

Under-FET Thermal Sensor Enabling Smart Full-Chip Run-Time Thermal Management

This article reports design, fabrication and analysis of a novel under-transistor (under-FET) in-hole thermal sensor diode structure. Being able to accurately monitor self-heating of individual transistor in-operando, the under-FET temperature sensor enables smart full-chip run-time thermal management with spatial resolution down to single transistor level. The in-hole thermal sensors were fabricated in a CMOS process and validated in measurements. The new chip level thermal management technique was demonstrated using a prototype power amplifier (PA) IC designed in a foundry 40nm CMOS. It opens a door for self-learning based full-chip real-time intelligent thermal management for future ICs

Programmable Synaptic Metaplasticity and below Femtojoule Spiking Energy Realized in Graphene-Based Neuromorphic Memristor

Memristors with rich interior dynamics of ion migration are promising for mimicking various biological synaptic functions in neuromorphic hardware systems. A graphene-based memristor shows an extremely low energy consumption of less than a femtojoule per spike, by taking advantage of weak surface van der Waals interaction of graphene. The device also shows an intriguing programmable metaplasticity property in which the synaptic plasticity depends on the history of the stimuli and yet allows rapid reconfiguration via an immediate stimulus. This graphene-based memristor could be a promising building block toward designing highly versatile and extremely energy efficient neuromorphic computing systems