Multi-objective evolutionary fuzzy clustering for high-dimensional problems

This paper deals with the application of unsupervised fuzzy clustering to high dimensional data. Two problems are addressed: groups (clusters) number discovery and feature selection without performance losses. In particular we analyze the potential of a genetic fuzzy system, that is the integration of a multi-objective evolutionary algorithm with a fuzzy clustering algorithm. The main characteristic of the integrated approach is the ability to handle the two problems at the same time, suggesting a Pareto set of trade-off solutions which could have a better chance of matching the real needs. We exhibit the high quality clustering and features selection results by applying our approach to a real-world data set

A Topology-Independent Mapping Technique for Application-Specific Networks-on-Chip

The design of Networks-on-Chip (NoCs) involves several key issues, including the topological mapping, that is, the mapping of the processing elements or Intellectual Properties (IPs) to the network nodes. Although several proposals have been focused on topological mapping last years, this topic is still an open issue. In this paper, we propose, in an extended manner, a topology-independent mapping technique for application-specific NoCs that can be used with regular or irregular topologies, and with any routing algorithm. This technique globally matches the communication pattern generated by the IPs with the available network bandwidth in the different parts of the network. The evaluation results show that the proposed technique can provide better performance than other mapping techniques not only in terms of average latency and network throughput, but also in terms of power consumption

Impact of Users' Beliefs in Text-Based Linguistic Interaction

Linguistic interaction between humans and machines is one of the most challenging fields in the development of next-generation User Interfaces. In this work, we investigate the role of beliefs about the interlocutor in human-computer linguistic interaction. First, we introduced an experimental setup that makes use of filtered and post-processed web content to generate a realistic, generic linguistic interaction. Then, we collected dialogues from two different sets α and β, corresponding to users being unaware or aware of the artificial nature of the interlocutor, respectively. The results thus obtained, analyzed using a standard t-test procedure (N=30), demonstrate a statistically significant difference between the two sets in some of the linguistic features selected, i.e., sentence length and the number of adjectives, providing further insights to expand some of the evidence previously found in the literature

smARTworks: A Multi-sided Context-aware Platform for the Smart Museum

n/

Coupling Routing Algorithm and Data Encoding for Low Power Networks on Chip

The routing algorithm used in a Network-on-Chip (NoC) has a strong impact on both the functional and non functional indices of the overall system. Traditionally, routing algorithms have been designed considering performance and cost as the main objectives. In this study we focus on two important non functional metrics, namely, power dissipation and energy consumption. We propose a selection policy that can be coupled with any multi-path routing function and whose primary goal is reducing power dissipation. As technology shrinks, the power dissipated by the network links represents an ever more significant fraction of the total power budget. Based on this, the proposed selection policy tries to reduce link power dissipation by selecting the output port of the router which minimises the switching activity of the output link. A set of experiments carried out on both synthetic and real traffic scenarios is presented. When the proposed selection policy is used in conjunction with a data encoding technique, on average, 31% of energy reduction and 37% of power saving is observed. An architectural implementation of the selection policy is also presented and its impact on cost (silicon area) and power dissipation of the baseline router is discussed

On Performance Optimization and Quality Control for Approximate-Communication-Enabled Networks-on-Chip

For many applications showing error forgiveness, approximate computing is a new design paradigm that trades application output accuracy for mitigating computation/communication effort, which results in performance/energy benefit. Since networks-on-chip (NoCs) are one of the major contributors to system performance and power consumption, the underlying communication is approximated to achieve time/energy improvement. However, performing approximation blindly causes unacceptable quality loss. In this article, first, an optimization problem to maximize NoC performance is formulated with the constraint of application quality requirement, and the application quality loss is studied. Second, a congestion-aware quality control method is proposed to improve system performance by aggressively dropping network data, which is based on flow prediction and a lightweight heuristic. In the experiments, two recent approximation methods for NoCs are augmented with our proposed control method to compare with their original ones. Experimental results show that our proposed method can speed up execution by as much as 29.42% over the two state-of-the-art works

Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package

The grand challenge of scaling up quantum computers requires a full-stack architectural standpoint. In this position paper, we will present the vision of a new generation of scalable quantum computing architectures featuring distributed quantum cores (Qcores) interconnected via quantum-coherent qubit state transfer links and orchestrated via an integrated wireless interconnect.Comment: 5 pages, 2 figures, accepted for presentation at the IEEE International Symposium on Circuits and Systems (ISCAS) 202

Design Challenges of Intra- and Inter- Chiplet Interconnection

In a chiplet-based many-core system, intra- and inter- chiplet interconnection is key to system performance and power consumption. There are a few challenges in intra- and inter- chiplet interconnection network: 1) Fast and accurate simulation is necessary to analyze the performance metrics. 2) Efficient network architecture for inter- and intra- chiplet is necessary, including topology, PHY design and deadlock free routing algorithms, etc. 3) Deep learning based AI systems are demanding more computation power, which calls for the need of efficient and low power chiplet-based systems. This paper proposes network designs to address these challenges and provides future research directions