Residue Number System Hardware Emulator and Instructions Generator

Residue Number System (RNS) is an alternative form of representing integers on which a large value gets represented by a set of smaller and independent integers. Cryptographic and signal filtering algorithms benefit from the use of RNS, due to its capabilities to increase performance and security. Herein, a simulation tool is presented which emulates the hardware implementation of an actual RNS co-processor. An “high-level to assembly” instructions generator is also built into this tool. The programmability and scalable architecture of the considered processor along with the high level description of the algorithm allows researchers and developers to easily evaluate and test their RNS algorithms on an actual architecture, using Java

Teaching hardware/software co-design using a project-based learning strategy

This paper presents a project-based learning strategy for teaching hardware/software co-design in modern Computer Engineering undergraduate courses. This kind of approach is considered by several recent pedagogical studies as the ideal strategy to support great learning achievements and to increase the proficiency of the students both in the design of digital systems and programming. The proposed strategy, targeting the first-year students, focuses on deepening the knowledge of combinatorial logic, sequential circuits, and state machines, alongside the hierarchical development of software, including for peripheral management.info:eu-repo/semantics/publishedVersio

A portable lab for the practical study of modern computer engineering

This demo paper presents the μLIC educational platform. μLIC makes available to the students of Digital Systems and Computer Architecture courses a quite simple, intuitive and portable hardware platform for the realization of their laboratory exercises. μLI C can also be used in other related courses, such as Embedded Systems or Hardware/Software Co-Design, which allows reducing the time needed to study the manuals of diverse development boards and tools and to concentrate the education towards the core contents of the courses. In addition, the low cost, diminished size, and portable nature of the μLIC boards enables students to carry a personal unit with them all the time to implement the class exercises also outside the classrooms, as well as hobby projects. In the demo, three typical lab assignments of Digital Systems, Computer Architecture, and Hardware/Software Co-Design courses are used to showcase the μLIC educational platform: a traffic light controller, a 4-bit Arithmetic and Logic Unit (ALU) and a mini Space Invaders inspired game, respectively.info:eu-repo/semantics/publishedVersio

An efficient scalable RNS architecture for large dynamic ranges

This paper proposes an efficient scalable Residue Number System (RNS) architecture supporting moduli sets with an arbitrary number of channels, allowing to achieve larger dynamic range and a higher level of parallelism. The proposed architecture allows the forward and reverse RNS conversion, by reusing the arithmetic channel units. The arithmetic operations supported at the channel level include addition, subtraction, and multiplication with accumulation capability. For the reverse conversion two algorithms are considered, one based on the Chinese Remainder Theorem and the other one on Mixed-Radix-Conversion, leading to implementations optimized for delay and required circuit area. With the proposed architecture a complete and compact RNS platform is achieved. Experimental results suggest gains of 17 % in the delay in the arithmetic operations, with an area reduction of 23 % regarding the RNS state of the art. When compared with a binary system the proposed architecture allows to perform the same computation 20 times faster alongside with only 10 % of the circuit area resources

A Compact and Scalable RNS Architecture

Conferência: IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)- Jun 05-07, 2013This paper proposes a unified architecture for designing Residue Number System (RNS) based processors for moduli sets with an arbitrary number of channels. Recently, new RNS moduli sets have been proposed in order to increase the dynamic range and reduce the width of the channels. The proposed architecture allows designing forward and reverse RNS converters, as well as the arithmetic operators of each modulo channel. The forward and reverse conversions are implemented using channel arithmetic units, resulting in a very compact architecture. Moreover, the arithmetic operations supported at the channel level include addition, subtraction, and multiplication with accumulation capability. The presented results suggest that the proposed RNS architecture leads to compact and scalable implementations, with competitive, or even better, performance when compared with the related state of the art, considering fixed moduli sets. Experimental results suggest gains of 17% in the delay of arithmetic operations, with an area reduction of 23% regarding the state of the art.IEEE; IEEE Comp So

Arithmetic-based binary-to-RNS converter modulo {2(n)+/- k} for jn-Bit dynamic range

In this brief, a read-only-memoryless structure for binary-to-residue number system (RNS) conversion modulo {2(n) +/- k} is proposed. This structure is based only on adders and constant multipliers. This brief is motivated by the existing {2(n) +/- k} binary-to-RNS converters, which are particular inefficient for larger values of n. The experimental results obtained for 4n and 8n bits of dynamic range suggest that the proposed conversion structures are able to significantly improve the forward conversion efficiency, with an AT metric improvement above 100%, regarding the related state of the art. Delay improvements of 2.17 times with only 5% area increase can be achieved if a proper selection of the {2(n) +/- k} moduli is performed

Virtual laboratory for educational environments

In this paper a new simulation environment for a virtual laboratory to educational proposes is presented. The Logisim platform was adopted as the base digital simulation tool, since it has a modular implementation in Java. All the hardware devices used in the laboratory course was designed as components accessible by the simulation tool, and integrated as a library. Moreover, this new library allows the user to access an external interface. This work was motivated by the needed to achieve better learning times on co-design projects, based on hardware and software implementations, and to reduce the laboratory time, decreasing the operational costs of engineer teaching. Furthermore, the use of virtual laboratories in educational environments allows the students to perform functional tests, before they went to a real laboratory. Moreover, these functional tests allow to speed-up the learning when a problem based approach methodology is considered. © 2014 IEEE

ROM-less RNS-to-binary converter moduli {22N − 1, 22N + 1, 2N − 3, 2N + 3}

In this paper, a novel ROM-less RNS-to-binary converter is proposed, using a new balanced moduli set {22n-1, 22n + 1, 2n-3, 2n + 3} for n even. The proposed converter is implemented with a two stage ROM-less approach, which computes the value of X based only in arithmetic operations, without using lookup tables. Experimental results for 24 to 120 bits of Dynamic Range, show that the proposed converter structure allows a balanced system with 20% faster arithmetic channels regarding the related state of the art, while requiring similar area resources. This improvement in the channel's performance is enough to offset the higher conversion costs of the proposed converter. Furthermore, up to 20% better Power-Delay-Product efficiency metric can be achieved for the full RNS architecture using the proposed moduli set. © 2014 IEEE