Low Cost, Efficient Output- Only Infrastructure Damage Detection with Wireless Sensor Networks

Sensor network comprises of sensors and actuators with universally useful processing components to agreeably screen physical or ecological conditions, for example, temperature, pressure, and so on. Wireless Sensor Networks are particularly portrayed by properties like the constrained power they can reap or store, dynamic network topology, expansive size of the arrangement. Sensor networks have an enormous application in fields which incorporates territory observing, object tracking, fire detection, landslide recognition and activity observing. Given the network topology, directing conventions in sensor networks can be named at based steering, various levelled based directing and area-based directing. Low Energy Adaptive Clustering Hierarchy (LEACH) is a vitality productive various levelled based steering convention. Our prime spotlight was on the examination of LEACH given specific parameters like network lifetime, soundness period, and so forth and furthermore the impact of particular sending assault and level of heterogeneity on LEACH convention

Design of Low-Complexity Hybrid Precoder and Inkjet-Printed Antenna Array for Massive MIMO Downlink Systems

The dramatically growing mobile communication industry necessitates the demand for the speedy and error-free connectivity at considerably low cost for the billions of users. This is made possible only through the technological advancements that replace the current 4G wireless systems by 5G. Massive MIMO is the key technology used in 5G that offers spectral efficiency of up to 3 times and throughput of up to 10 times the current 4G. The additional antennas used in massive MIMO systems help in many ways but lack in complexity. Hence, in this paper, we propose two design methodologies to reduce the complexity of massive MIMO systems. The first one is the design of low-complexity hybrid precoder based on Zero-Forcing (ZF) precoding algorithm and Neumann series approximation. The second one is the design of flexible, environment friendly, simple 128-element antenna array at the frequency of 2.4 GHz using inkjet printing technology. The substrate used for printing is the “glossy paper” with dielectric constant of 2.31, and the ink used is silver nanoparticle ink with conductivity of 35,700,000 s/m. The element used for the formation of array is the z-shaped coplanar waveguide (CPW) monopole antenna. The performance of the proposed designs is evaluated in terms of probability of error for the hybrid precoding algorithm and radiation characteristics like gain, directivity, and return loss for the printed antenna design

VLSI Architecture for High Performance 3GPP Interleaver/Deinterleaver for Turbo Codes

Interleaving along with error correction coding is an effective way to deal with different types of error in digital data communication. Error burst due to multipath fading and from other sources in a digital channel may be effectively combated by interleaving. Normally the interleaver / deinterleaver pair is often designed as reconfigurable architectures able to deal with requirements of large data length variability found in the newest communication standards. In this work reconfigurable interleaver architecture for the turbo decoder in 3rd Generation Partnership Project (3GPP) standard is presented. The interleaver is a key component of radio communication systems. Using conventional design methods, it consumes a large part of silicon area in the design of turbo encoder and decoder. The proposed interleaver utilizes the algorithmic level hardware simplifications and generates 100 manage the ow of data streams to achieve very low cost solution. The proposed technique reduces consumption of FPGA resources to a large extent compared with existing state-ofthe-art interleaver for turbo codes. The proposed architecture con- sumes only 4856 logic elements by hardware optimization

An Efficient VLSI Architecture for Primary Synchronization Signal Detector

ABSTRACT: In this paper, we present a novel design for the detection of primary synchronization signal in a Long Term Evolution (LTE) system based device at the expense of low cost and low power. This is facilitated by using a matched filter architecture which incorporates parallel processing. The approach of a 1-bit analog-to-digital converter (ADC) with down-sampling is compared with that of a 10-bit ADC without down-sampling under multi-path fading conditions defined in LTE standard for user equipment (UE) performance test. A high performance primary synchronization signal detection method is derived in this paper