Low-Energy Proton Testing Methodology

Use of low-energy protons and high-energy light ions is becoming necessary to investigate current-generation SEU thresholds. Systematic errors can dominate measurements made with low-energy protons. Range and energy straggling contribute to systematic error. Low-energy proton testing is not a step-and-repeat process. Low-energy protons and high-energy light ions can be used to measure SEU cross section of single sensitive features; important for simulation

Field dependent dopant deactivation in bipolar devices at elevated irradiation temperatures

Dopant deactivation at 100 C is measured in bipolar Si-SiO{sub 2} structures as a function of irradiation bias. The deactivation occurs most efficiently at small biases in depletion and is consistent with passivation and compensation mechanisms involving hydrogen

Fiscal Year 1999

This project represented a coordinated LLNL-SNL collaboration to investigate the feasibility of developing radiation-hardened magnetic non-volatile memories using giant magnetoresistance (GMR) materials. The intent of this limited-duration study was to investigate whether giant magnetoresistance (GMR) materials similar to those used for magnetic tunnel junctions (MTJs) were process compatible with functioning CMOS circuits. Sandia's work on this project demonstrated that deposition of GMR materials did not affect the operation nor the radiation hardness of Sandia's rad-hard CMOS technology, nor did the integration of GMR materials and exposure to ionizing radiation affect the magnetic properties of the GMR films. Thus, following deposition of GMR films on rad-hard integrated circuits, both the circuits and the films survived ionizing radiation levels consistent with DOE mission requirements. Furthermore, Sandia developed techniques to pattern deposited GMR films without degrading the completed integrated circuits upon which they were deposited. The present feasibility study demonstrated all the necessary processing elements to allow fabrication of the non-volatile memory elements onto an existing CMOS chip, and even allow the use of embedded (on-chip) non-volatile memories for system-on-a-chip applications, even in demanding radiation environments. However, funding agencies DTRA, AIM, and DARPA did not have any funds available to support the required follow-on technology development projects that would have been required to develop functioning prototype circuits, nor were such funds available from LDRD nor from other DOE program funds

Actively Biased p-Channel MOSFET Studied with Scanning Capacitance Microscopy

Scanning capacitance microscopy (SCM) was used to study the cross section of an operating p-channel MOSFET. We discuss the novel test structure design and the modifications to the SCM hardware that enabled us to perform SCM while applying dc bias voltages to operate the device. The results are compared with device simulations performed with DAVINCI

Proton-Induced Upsets in SLC and MLC NAND Flash Memories

We investigate proton-induced upsets in state-of-the-art NAND Flash memories, down to the 25-nm node. The most striking result is the opposite behavior of Multi-Level Cell (MLC) and Single-Level Cell (SLC) devices, in terms of floating gate error cross section as a function of proton energy. In fact, the cross section increases with proton energy in SLC whereas it decreases in MLC. The reason for this behavior is studied through comparison of heavy-ion data and device simulations. The main factors that determine proton energy dependence are discussed, such as the energy dependence of nuclear cross section between protons and chip materials, the LET, energy, and angular distributions of the generated secondaries, but also the heavy-ion and total dose response of the studied devices. Proton irradiation effects in the control circuitry of NAND Flash memories are shown as well

Field Dependent Dopant Deactivation in Bipolar Devices at Elevated irradiation Temperatures

Metal-oxide-silicon capacitors fabricated in a bi-polar process were examined for densities of oxide trapped charge, interface traps and deactivated substrate acceptors following high-dose-rate irradiation at 100 C. Acceptor neutralization near the Si surface occurs most efficiently for small irradiation biases in depletion. The bias dependence is consistent with compensation and passivation mechanisms involving the drift of H{sup +} ions in the oxide and Si layers and the availability of holes in the Si depletion region. Capacitor data from unbiased irradiations were used to simulate the impact of acceptor neutralization on the current gain of an npn bipolar transistor. Neutralized acceptors near the base surface enhance current gain degradation associated with radiation-induced oxide trapped charge and interface traps by increasing base recombination. The additional recombination results from the convergence of carrier concentrations in the base and increased sensitivity of the base to oxide trapped charge. The enhanced gain degradation is moderated by increased electron injection from the emitter. These results suggest that acceptor neutralization may enhance radiation-induced degradation of linear circuits at elevated temperatures

Single-event upset and snapback in silicon-on-insulator devices

SEU is studied in SOI transistors and circuits with various body tie structures. The importance of impact ionization effects, including single-event snapback, is explored. Implications for hardness assurance testing of SOI integrated circuits are discussed

New Insights into Fully-Depleted SOI Transistor Response During Total-Dose Irradiation

Previous work showed the possible existence of a total-dose latch effect in fully-depleted SOI transistors that could severely limit the radiation hardness of SOI devices. Other work showed that worst-case bias configuration during irradiation was the transmission gate bias configuration. In this work we further explore the effects of total-dose ionizing irradiation on fully-depleted SOI transistors. Closed-geometry and standard transistors fabricated in two fully-depleted processes were irradiated with 10-keV x rays. Our results show no evidence for a total-dose latch effect as proposed by others. Instead, in absence of parasitic trench sidewall leakage, our data suggests that the increase in radiation-induced leakage current is caused by positive charge trapping in the buried oxide inverting the back-channel interface. At moderate levels of trapped charge, the back-channel interface is slightly inverted causing a small leakage current to flow. This leakage current is amplified to considerably higher levels by impact ionization. Because the back-channel interface is in weak inversion, the top-gate bias can modulate the back-channel interface and turn the leakage current off at large, negative voltage levels. At high levels of trapped charge, the back-channel interface is fully inverted and the gate bias has little effect on leakage current. However, it is likely that this current also is amplified by impact ionization. For these transistors, the worst-case bias configuration was determined to be the ''ON'' bias configuration. These results have important implication on hardness assurance

Thermal-stress effects on enhanced low-dose-rate sensitivity of linear bipolar circuits

Thermal-stress effects are shown to have a significant impact on the enhanced low-dose-rate sensitivity of linear bipolar circuits. Implications of these results on hardness assurance testing and mechanisms are discussed