Dodd, P. E.

Schwank, James R.

Shaneyfelt, Marty R.

Walsh, David S.

UNT Digital Library

1Investigation of Body-Tie Effects on Ion Beam Induced Charge Collection in Silicon-On-Insulator FETs using the Sandia Nuclear Microprobe.David S. Walsh, P. E.Dodd, M. R. Shaneyfelt, and J. R. Schwank.Sandia National Laboratories, P.O. ~ox 5800 Albuquerque, NM USA 87185-1056Keywords: SOI, body-tie design, single event effectsPACS codes: 61.82.Jh, 85.30.Tv, 61.16.YcSilicon-on-insulator (S01) technology exhibits three main advantages over bulk silicontechnology for use in radiation environments. (1) SOI devices are immune to Iatchup, (2)thevolume of the sensitive region (body) and hence total charge collection per transient irradiationis much reduced in SOI devices and (3) the insulating layer blocks charge collection from thesubstrate (i.e., no fimneling effect). This effectively raises the single event upset threshold forthe SOI device. However, despite their small active volume SOI devices are still vulnerable tosingle event effects (SEE). Inherent in the SOI transistor design is a parasitic npn bipolarjunction transistor (BJT), where the source-body-drain acts as an emitter-base-collector BJT. Anion strike to a floating (not referenced to a specific potential) body can create a condition calledsnapback, where excess minority carriers in the drain-body junction forward bias the source-body junction, causing the parasitic BJT to turn on and inject current into the drain. Tying thebody to the source limits the emitter-base current and reduces the sensitivity of the device tosingle ion strikes. Unfortunately, the body-tie loses effectiveness with distance due toresistivity, and in regions far enough from the tie the BJT is still in effect.Using the Sandia nuclear microprobe we have created charge collection maps of SOIFETs which have different body-tie designs. Comparisons of the experiment to DAVINCIsimulations are also presented. Effects of body-ties and operating voltage on snap-backthresholds are also presented and predictions of performance in radiation environments madefor the different designs.Reference: ME-02Contact: David S. WalshSandia National LaboratoriesP.O. BOX 5800Albuquerque, NM USA 87185-1056Phone: 505-844-9590 fax: 505-844-7775Email: dswalsh@sandia.govDISCLAIMERThis report was prepared as an account of work sponsoredby an agency bf the United States Government. Neitherthe United States Government nor any agency thereof, norany of their employees, make any warranty, express orimplied, or assumes any legal liability or responsibility forthe accuracy, completeness, or usefulness of anyinformation, apparatus, product, or process disclosed, orrepresents that its use would not infringe privately ownedrights. Reference herein to any specific commercialproduct, process, or service by trade name, trademark,manufacturer, or otherwise does not necessarily constituteor imply its endorsement, recommendation, or favoring bythe United States Government or any agency thereof. Theviews and opinions of authors expressed herein do notnecessarily state or reflect those of the United StatesGovernment or any agency thereof.DISCLAIMERPortions of this document may be illegiblein electronic image products. Images areproduced from the best available originaldocument.? . 121. IntroductionIn the last twenty-five years single event effects (SEE) have become a major concern forthe operators of microelectronic ‘devices in elevated radiation environments, as is the case fororbital or high altitude electronic system.. The extremely high density of electron-hole pairscreated along the path of an incident high-energy ion strike distorts the electric fields in asemiconductor device in a manner which extends the depletion region well into the substrateof the device. This .in turn causes large amounts of charge to be collected from a relativelylong section (on the order of tens of micrometers) of that path via both drifi and diffusivecollection mechanisms. This is the well-known “fimnel effect” first described nearly twentyyears ago [1] and illustrated in Fig. 1a. At the circuit level this ion-induced charge can causevarious problems including a change of memory state (single event upset or SEU), latchup(SEL) or even permanent damage (“hard’ failures) such as gate rupture (SEGR) [2].A very popular and efllcient method of “hardening” semiconductors against SEE is toreduce the volume fi-om which ion-induced charge can be collected through the use ofsilicon-on-insulator (S01) technologies[3]. In these technologies the active regions of thesemiconductor are fabricated in a thin, top layer of silicon which is separated from the siliconsubstrate by a buried insulating layer, most commonly silicon dioxide (sapphire is also used).The thickness of the active film region determines the SOI transistor mode of operation: fillydepleted, partially depleted or “bulk-like”. Fig. 2a shows a typical partially depleted n-channel SOI MOSFET (metal-oxide-silicon field effect transistor). The top (active) siliconregion is generally the thickness of the original wafer (150-300 nm) and the heavily dopedsource and drain regions extend the entire depth of the silicon to border directly upon theburied oxide. The buried oxide is generally on the order of 300 m-n thick. While the mode of, ,preparation of the buried oxide is importmt for total radiation dose effects, it is not pertinentto SEE which only depend upon the geometry and doping of the electrically active top siliconregion. This particuhr technolo~y aIso employs shallow trench isolation to reduce lateralparasitic bipolar effects in the CMOS inverter structure. In this type of SOI transistor thegate voltage does not deplete the entire depth of the active region underneath the gate (knownas the “body” region), the conductive channel being created only at the top of the body film –hence the name “partially depleted” SOI (PD-SOI).One of the benefits of this design for mitigating SEE is illustratedand ion strike to a PD-SOI transistor. In contrast to bulk silicon (Fig.buried oxide layer does not allow charge generated in the substrate toin Fig. 1b which shows1a), the insulatingbe collected by theelectrically active junctions in the thin top region of the device. The only electrons collectedare those actually produced within the top silicon region. This order of 50x reduction incharge collection depth from about 10 pm in bulk silicon to a few hundred nm in PD-SOIshould result in a much higher SEU threshold (a measure of the amount of charge depositionneeded to cause SEU) for SOI technology when compared to bulk silicon [4,5].A second benefit of SOI design is the reduced area of p-n junctions in the transistor ascompared to bulk designs. The source and drain regions extend the entire depth of the siliconfilm to the buried oxide and hence have no depletion regions underneath them (as do exist inbulk silicon). The only depletion regions which exist in the PD-SOI transistor are betweenthe body and the heavily doped source and drain regions. This reduced p-n junction arealeads to significant reductions in SEU cross-section (a measure of the SEU sensitive area) forSOI integrated circuits (ICS) compared to bulk silicon [5].< !4Unfortunately, a bipolar charge amplification mechanism (illustrated in Fig. 2b) existswithin SOI MOSFETS which maybe the limiting factor in their SEU performance. Thecurrent generated by an ion strik~ to the body region of a partially depleted SOI MOSFETcan be amplified by the parasitic bipolar junction transistor (BJT) inherent in the device(source/body/drain = emitter/base/collector). In the n-channel SOI transistor case forexample the electrons generated in the body by an ion strike are quickly swept into the drainand source leaving the holes behind. These holes raise the body potential (known as FloatingBody Effect or FBE) and forward bias the inherent lateral parasitic BJT (n-source/p-body/n-drain). This bipolar effect will amplifi the charge collected at the drain by an amount equalto the current gain ~ of the parasitic BJT (i.e., Q.= (1+ fl)Qi where Q, is the chargecollected at the drain and Q is the charge induced by the incident ion). /? increases withdecreasing channel length, to the point that very short SOI transistors could be more sensitiveto SEU than bulk devices [3]. In an extreme case the FBE can trigger a high current stateknown as single event snapback (SES – sometimes also known as single transistor latch) ifthe channel conduction is sustained by regenerative impact ionization effects near the body-drain junction [6,7]. Impact ionization is the creation of more electron-hole pairs by theelectron current in the body region. Snapback requires both a minimum potential differencebetween source and drain (the threshold drain voltage) and a source of electrons in thechannel. These can be supplied either by an ion strike or electrically, by operation of the gateto open the channel.Reduction of FBE is therefore key to achieving SEE resistant SOI technology. To reduceFBE SOI transistors are designed with body ties which hold the body region at a fixedpotential (usually the source potential) [3]. Effective body tie design is an extremely,5important feature for realizing SEE hard circuits in SOI. Effectiveness of the body-tieincreases as separation of the tie from the ion strike location decreases. In this paper we usefocused heavy ion microbeam e~periments, electrical testing and 3D numerical simulationsto study charge collection and snapback in PD-SOI transistors with different body tieparameters. Impact ionization and SES are shown to be important effects in submicronlength n-channel SOI devices. The results have implications for radiation hardness testing ofSOI technologies.2. ExperimentA. Test DevicesThe devices tested in this report are body-tied, n-channel PD-SOI transistors designedand fabricated at Sandia’s Microelectronic Development Laboratory using the 5V CMOS6rsprocess (includes shallow trench isolation for radiation hardening). The FETs hale a drawngate-length of 0.6 mm, a gate-oxide thickness of 12.5 nm, a buried oxide thickness of -370nm and an active silicon region thickness of-170 nm. Transistors with body channel w’idthsvarying from 20 to 1.1 Pm were tested.B. Body TiesThe body ties tested to date are conventional body-tied-to-source (BTS) configurations asillustrated in Fig. 3. The body is independently tied at both ends of the channel by p-typeregions which are shorted directly to the source by silicidation. The distance between the p+body tie and the channel is about 0.5 Pm for these CMOS6rs transistors.C. MeasurementsElectrical characterization of snapback in this technology was performed using an HP4062 parametric analyzer. The drain current (ld,) was measured aS the gate voltage ( Vg,) was.6swept from accumulation to depletion (negative to positive for n-channel transistors) atdifferent drain biases (J’’&). The lowest V~~for which 1A remained high at zero gate voltagewas considered the SES threshold voltage ( VA@’ES)). Systematic measurements of ion-induced snapback threshold drain voltage as a finction of body width were made on theSandia nuclear microprobe by sc&ning focused 35 MeV Cl+bor 40 MeV CU+7ions over thedevice under test while monitoring the drain power supply current. In additionalexperiments, 1~and body (lb) ion-induced transients from 28 MeV Si+s or 40 MeV CU+7impacts were simultaneously recorded using our time-resolved-ibicc (TRIBICC) system witha 1- GHz TEK680 digitizer (9). This system allows us to scan the ion beam over the FETand collect up to 64x64 point maps of device response while minimizing damage to theactive region by (1) storing one complete transient per ion strike, and (2) deflecting the beamaway during the period the system requires to digitize and store each transient (-O. 1 to 1s).D. SimulationsSimulations were performed using the three-dimensional device/circuit simulator Davinci(1O). Simulations of both transistor response and circuit level SEU have been performed.An impact-ionization model is included in Davinci; its impact upon results was tested byperforming some simulations both with and without the model active.3. Results and DiscussionsResults of the SES drain voltage (Vd@,E$)) threshold measurements are shown in Fig. 4.Included are plots of the measured VdJSES) versus gate width for 35 MeV Cl+bimpacts(surface LET of around 18 MeV-cmz/mg), 40 MeV CU+7 (surface LET of around 29 MeV-.7cm2/mg) impacts and electrical sweeps. It is interesting to note that the V&(SES) threshold isextremely similar for all three conditions. This, along with the fact that using 20 MeV C+3ions we were not able to initiate !napback at all in these devices, suggests that SES exhibitssaturation behavior; once an ion strike (or electrical opening of the channel) can supply acertain amount of cha-ge to the body region, snapback is initiated. A higher LET particlewhich deposits more charge will not significantly alter the voltage threshold. This isconsistent with electrical response in that once the snapback condition is initiated, raising Vgsmore does not lower the snapback drain voltage threshold. This finding may have positiveimplications for fhture snapback mitigation efforts in that susceptibility to heavy-ion SESmay well be predictable with electric testing. Note in Fig. 4 that thresholds predicted usingthe Davinci simulator for several channel widths also match \vith experiment. Simulations ofdevices with other channel widths are pending.Since the body tie effect is limited by the channel resistance. these transistors should bemost sensitive to ion-induced SES at the center of the body, farthest from the contacts at bothends of the channel. Fig. 5 shows a plot of the charge collected at the drain following the ionstrike of focused (-1 Pm resolution in scan direction) , 40 MeV CU*7asacross the width of a 0.6x20 Pm channel. The drain was biased at 5.3Vthe beam is scanned(above the SESthreshold) through a capacitively de-coupled bias tee. Strikes to the center four microns ofthe body induce SES which result in drain currents on the order of 1 rnA . Strikes outsidethis central region are close enough to the body-ties that the bipolar amplification effect ismore limited and regenerative impact-ionization levels are not reached. We have plottedhere the charge integrated over 72 ns following the ion strike. In our system the bias teecapacitor is discharged over the course of a microsecond or so, which then draws the drain‘.8bias voltage back below the SES threshold and terminates the snapback current. This is avery usefil feature for producing SES maps in a timely manner with the microbeam. Typical“sub-snapback” current transients last on the order of a nanosecond in this system.The effect of the BTSon the bipolar amplification of QI, the charge injected into thebody, is illustrated in Fig. 6 for 28 MeV Si+5ion strikes on a 0.6x20 %-ndevice. Q=, thecharge collected at the drain is approximately equal to Q near the contact, but is almosttwice Q for ion strikes near the center of the body at the firthest point from the BTS. Asdevices scale downward in size the increased bipolar amplification to expected from shorterchannel lengths should be mitigated somewhat by the increased effectiveness of body tiesdue to narrower channel widths.4. SummaryWe have used the Sandia heavy-ion nuclear microprobe to induce single event snapbackin SOI transistors. We have measured the inverse effect of distance from the body-tie (i.e.channel width) on SES drain voltage thresholds and bipolar charge amplification in the bodyregion. In the future we will reproduce these type of measurements and simulations ondevices with varying gate lengths to check for changing bipolar effects and on Body-Under-Source (BUSFET) tie designs where the source does not extend all the way to the buriedoxide and the body contact runs under the entire width of the source. This effectively placesthe contact much closer to the channel. These devices are predicted to have much better SESresistance.Acknowledgement: The authors would like to acknowledge the excellent technical assistance of Daniel Buller andGerald Hash in producing this work. Sandia is a multiprogram laboratory operated by Sandia Corporation, aLockheed Martin Company. for the United States Department of Energy under contract DE-AC04-94A185000.9tReferences101. C. M. Hsieh, P. C. Murley and R. R. O’Brien, IEEE Electron Dev. Lett. 2 (1981)103.2. G. C. Messenger and M. S. Ash, Single Event Phenomena (New York, Chapmanand Hall, 1997).3. J. P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI 2nd ed.(Boston, Kluwer Academic, 1997).4. G. E. Davis et al., IEEE Trans. Nucl. Sci. 32 (1985) 4432.5. J. L. Leray et al., IEEE Trans. Nucl. Sci. 35 (1988) 1355.6. R. Koga and W. A. Kolasinski, IEEE Trans. Nucl. Sci. 36 (1989) 2367.7. 0. Musseau, J. L. Leray, V. Ferlet, A. Umbert, Y. M. Coic and P. Hesto, IEEETrans. Nucl. Sci. 38 (1991) 1226.8. L. R. Hite et al., IEEE Trans. Nucl. Sci. 39 (1992) 2121.9. H. Schone, et al., NIM B 158 (1999) 424.10. Davinci 1992.2, Avant! Corporation, (1999)Figure Captions111. Ion penetration of a bulk (a) and an SOI (b) device. In SOI the buried insulatinglayer prevents charge generated in the substrate from being collected by thejunctions of the device. After Colinge (3).2. (a) Cross-section diagram of a typical partially depleted SOI n-channel transistor.(b) Holes created by an ion strike in the body region raise the body potential“ relative to the source. This activates the parasitic source/body/drain bipolartransistor which amplifies current to the drain. If the drain voltage is high enoughthe electrons in the channel can create more e-h pairs at the drain junction byimpact ionization.3. Plan view of test device body ties. The channel is tied at both ends by a singlesilicide region which forms both the body and source contact. Dotted linesindicate contact regions.4. Measured and simulated SES threshold drain voltages as a function of gate widthfor CMOS6rs n-channel transistors. Simulations are for 35 MeV Cl-j ion strikes.The similar threshold values for 40 MeV Cu (LET-29), 35 MeV Cl (LET-1 7)and electrically-induced SES suggest a saturation behavior to snapback.5. Drain charge collected from 40 MeV CU+7strikes at different locations across thewidth of a 0.6x20 Pm body. Due to resistance in the channel the effectiveness ofthe body-tie at preventing SES diminishes with distance from the contact points atboth ends of the body..126. Drain charge collected versus distance from the body- tie contact. For strikes nearthe body-tie floating body effects are limited and the bipolar amplification of thecharge is reduced. 1Bulk/sol/I p+ Substrate IaFig. 1bCMOSISOIt-170 nmt --370 nm+SubstrateFig. 2a,soco.-%N.-S0.0●(\● o).. Onm‘i.-k.m.3c).—z.. ........ .I‘,/.so.—T.—;m0m,. ........,., ..m&.-k“II I I I-aU)gsoo—snc)coK@(xlI , I t I IoNmou)o‘E’oL■ Eud-glLL%a) L/3.-. . ,)mo.-.—.—.—— —Distance from Body-Tie Effects Bipolar Amplification of10090I 80c.-(uIi706050403020Charge40 MeV Cu, 0.6x20 ~LmBody_——- —._... .-—A A~A■ ————+A■Bipolar AmplificationDrift Collection1000 2 4 6 8 10 ‘t23.02.5 ‘o.-Z2.0 Iyua),-1,5 ~:a1.0 +ja)=s0.50.0I Distance to Body Contact (ILM)I . . ....

Investigation of Body-Tie Effects on Ion Beam Induced Charge Collection in Silicon-On-Insulator FETs Using the Sandia Nuclear Microprobe

Abstract

Similar works

Full text

Available Versions

UNT Digital Library